MC88915FN70 IDT, Integrated Device Technology Inc, MC88915FN70 Datasheet - Page 11

• Manufacturer Part Number: MC88915FN70
• Description: IC PLL CLOCK DRIVER 28-PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Driverr

Specifications of MC88915FN70

• Pll: Yes with Bypass
• Input: TTL
• Output: CMOS, TTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:8
• Differential - Input:output: No/No
• Frequency - Max: 70MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Frequency-max: 70MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

IDT™ / ICS™ CMOS PLL CLOCK DRIVERS
MC88915
LOW SKEW CMOS PLL CLOCK DRIVERS
NOTES CONCERNING LOOP FILTER AND BOARD LAYOUT ISSUES
1.
Figure 8
scheme which will be effective in most applications. The
following guidelines should be followed to ensure stable
and jitter-free operation:
a.
b.
FREQUENCY
10 µF LOW
BYPASS
All loop filter and analog isolation components
should be tied as close to the package as possible.
Stray current passing through the parasitics of long
traces can cause undesirable voltage transients at
the RC1 pin.
The 47 Ω resistors, the 10 µF low frequency bypass
capacitor, and the 0.1 µF high frequency bypass
capacitor form a wide bandwidth filter minimizing
the 88915’s sensitivity to voltage transients from
the system digital V
This filter will typically ensure a 100 mV step
deviation on the digital V
more than a 100 ps phase deviation o the 88915
outputs. A 250 mV step deviation on V
recommended filter values should cause no more
than 250 ps phase deviation; if a 25 µF bypass
capacitor is used (instead of 10 µF) a 250 mV V
step should cause no more than a 100 ps phase
deviation.
If good bypass techniques are used on a board
design near components potentially causing digital
V
step deviations should not occur at the 88915’s
CC
shows a loop filter and analog isolation
and ground noise, the above described V
Figure 8. Recommended Loop Filter and Analog Isolation Scheme for the MC88915
FREQUENCY
0.1 µF HIGH
CC
BYPASS
supply and ground planes.
CC
supply, causing no
470 kΩ
CC
47 Ω
1 MΩ
47 Ω
BOARD V
OR
BOARD GND
using the
CC
CC
0.1 µF (LOOP
FILTER CAP)
CC
330 Ω
NOTE:
11
2.
A separate analog power supply is not necessary and
should not be used. Following these prescribed guidelines
is all that is necessary to use the MC88915 in a normal
digital environment.
c.
d.
In addition to the bypass capacitors used in the analog
filter of
capacitor between each of the other (digital) four V
pins and the board ground plane. This will reduce output
switching noise caused by the 88915 outputs, in
addition to reducing potential for noise in the “analog”
section of the chip. These bypass capacitors should
also be tied as close to the 88915 package as possible.
10
8
9
digital V
filtering scheme shown in
88915 additional protection from the power supply
and ground plane transients potentially occurring in
a high frequency, high speed digital system.
There are no special requirements set forth for the
loop filter resistors (1 MΩ or 470 KΩ and 330 Ω).
The loop filter capacitor (0.1 µF) can be a ceramic
chip capacitor, the same as a standard bypass
capacitor.
The 1 MΩ or 470 KΩ reference resistor injects
current into the internal charge pump of the PLL,
causing a fixed offset between the outputs and the
SYNC input. This also prevents excessive jitter
caused by inherent PLL dead-band. If the VCO
(2X_Q output) is running above 40 MHz, the 470
KΩ resistor provides the correct amount of current
injection into the charge pump (2–3 µA). if the VCO
is running below 40 MHz, a 1.0 MΩ reference
resistor should be used (instead of 470 KΩ).
ANALOG V
RC1
ANALOG GND
Figure
CC
8, there should be a 0.1 µF bypass
CC
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88915
28-PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
supply. The purpose of the bypass
Figure 8
MC88915 REV 6 JULY 10, 2007
is to give the
CC