IDT5T2010BBI IDT, Integrated Device Technology Inc, IDT5T2010BBI Datasheet - Page 5

• Manufacturer Part Number: IDT5T2010BBI
• Description: IC CLK DVR ZD PLL 2.5V 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: TeraClock™r
• Type: PLL Clock Driverr

Specifications of IDT5T2010BBI

• Pll: Yes with Bypass
• Input: eHSTL, HSTL, LVPECL, LVTTL
• Output: eHSTL, HSTL, LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: Yes/No
• Frequency - Max: 250MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 5T2010BBI

PIN DESCRIPTION, CONTINUED
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate V
3. 3-level inputs are static inputs and must be tied to V
OUTPUT ENABLE/DISABLE
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
POWERDOWN
NOTE:
1. PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
IDT5T2010
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK
REF_SEL
OMODE
Symbol
PLL_EN
FBF
DS
LOCK
nQ
nQ
LOW/HIGH state.
nQ
nsOE
nF
GND
V
QFB
QFB
RxS
TxS
V
PE
FS
PD
DDQ
[1:0]
[1:0]
DD
[2:1]
[1:0]
[1:0]
[2:1]
nsOE
is stopped in a HIGH/LOW state.
and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a
PD
H
H
H
L
L
L
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Adjustable
Adjustable
Adjustable
3-Level
3-Level
3-Level
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Type
PWR
PWR
PWR
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(3)
(3)
(3)
OMODE
OMODE
(2)
(2)
(2)
H
H
X
X
L
L
Description
Reference clock select. When LOW, selects REF
Synchronous output enable. When nsOE is HIGH, nQ
LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH, the
nQ
Feedback clock output
Complementary feedback clock output
Five banks of two outputs
Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL/eHSTL (LOW)
compatible. Used in conjuction with V
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank (See Control Summary table)
Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
Selects appropriate oscillator circuit based on anticipated frequency range. (See VCO Frequency Range Select.)
3-level inputs for feedback input divider selection (See Divide Selection table)
PLL enable/disable control. Set LOW for normal operation. When PLL_EN is HIGH, the PLL is disabled and REF
Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ
LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
Output disable control. Determines the outputs' disable state. Used in conjunction with nsOE and PD. (See Output Enable/Disable and
Powerdown tables.)
Power supply for output buffers. When using 2.5V LVTTL, V
Power supply for phase locked loop, lock output, inputs, and other internal circuitry
Ground
[1:0]
is stopped in a HIGH/LOW state. When OMODE is LOW, the outputs are tri-stated. Set nsOE LOW for normal operation.
DD
[1:0]
or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
and QFB are stopped in a HIGH/LOW state, while the QFB is stopped in a LOW/HIGH state. When OMODE is
Normal Operation
Normal Operation
Tri-State
Gated
Tri-State
Gated
Output
Output
(1)
(1)
DDQ
to set the interface levels.
5
VCO FREQUENCY RANGE SELECT
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
0
and REF
VCO. The VCO frequency (F
operated in their undivided modes. The frequency appearing at the REF
REF
are undivided and DS
and FB and FB/V
frequency multiplication by using a divided QFB and QFB and setting DS
Using the DS
Divide Selection table).
[1:0]
HIGH
FS
LOW
[1:0]
are synchronously stopped. OMODE selects whether the outputs are gated
(1)
DDQ
/V
0
REF
/V
should be connected to V
REF
[1:0]
[1:0]
0.
REF
inputs allows a different method for frequency multiplication (see
and FB and FB/V
When HIGH, selects REF
2 inputs will be F
[1:0]
Min.
100
50
= MM. The frequency of REF
NOM
DDQ
INDUSTRIAL TEMPERATURE RANGE
) always appears at nQ
REF
voltage.
NOM
2 inputs will be F
DD.
/2 or F
Max.
1
125
250
NOM
and REF
/4 when the part is configured for
NOM
1
[1:0]
[1:0]
/V
[1:0]
when the QFB and QFB
REF
outputs when they are
and REF
goes to all outputs.
1.
MHz
MHz
Unit
[1:0]
[1:0]
[1:0]
/V
REF
= MM.
and
[1:0]