CY7B991V-5JI Cypress Semiconductor Corp, CY7B991V-5JI Datasheet - Page 15

• Manufacturer Part Number: CY7B991V-5JI
• Description: IC CLK BUFF SKEW 8OUT 32PLCC
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Zero Delay Bufferr
• Series: RoboClock+™r

Specifications of CY7B991V-5JI

• Number Of Circuits: 1
• Package / Case: 32-PLCC
• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Ratio - Input:output: 1:8
• Differential - Input:output: No/No
• Frequency - Max: 80MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 80MHz
• Output Frequency Range: 3.75 MHz to 80 MHz
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

range since the highest frequency output is running at 20 MHz.
Figure 9
3Qx and 4Qx outputs. These include inverted outputs and
outputs that offer divide-by-2 and divide-by-4 timing. An inverted
output enables the system designer to clock different
subsystems on opposite edges, without suffering from the pulse
asymmetry typical of non-ideal loading. This function enables
each of the two subsystems to clock 180 degrees out of phase
and align within the skew specifications.
The divided outputs offer a zero delay divider for portions of the
system that need the clock divided by either two or four, and still
remain within a narrow skew of the “1X” clock. Without this
feature, an external divider is added, and the propagation delay
Document Number: 38-07138 Rev. *E
DISTRIBUTION
20 MHz
CLOCK
shows some of the functions that are selectable on the
FB
REF
FS
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
TEST
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
Figure 9. Multi-Function Clock Driver
REF
of the divider adds to the skew between the different clock
signals.
These divided outputs, coupled with the Phase Locked Loop,
enables the PSCB to multiply the clock rate at the REF input by
either two or four. This mode enables the designer to distribute
a low frequency clock between various portions of the system,
and then locally multiply the clock rate to a more suitable
frequency, still maintaining the low skew characteristics of the
clock driver. The PSCB performs all of the functions described in
this section at the same time. It multiplies by two and four or
divides by two (and four) at the same time. In other words, it is
shifting its outputs over a wide range or maintaining zero skew
between selected outputs.
SKEWED –3.125 ns (–4t
80 MHz
ZERO SKEW
INVERTED
80 MHz
20 MHz
80 MHz
U
)
Z
0
Z
Z
0
Z
0
0
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CY7B991
CY7B992
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