MK2069-04GILFTR IDT, Integrated Device Technology Inc, MK2069-04GILFTR Datasheet - Page 8

• Manufacturer Part Number: MK2069-04GILFTR
• Description: IC VCXO CLK TRANSLATOR 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Synchronizerr

Specifications of MK2069-04GILFTR

• Pll: Yes
• Input: LVCMOS
• Output: LVCMOS
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 160MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 160MHz
• Number Of Elements: 2
• Supply Current: 30mA
• Pll Input Freq (min): 1KHz
• Pll Input Freq (max): 170MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSSOP
• Output Frequency Range: 0.5 to 160MHz
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Operating Temperature Classification: Industrial
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

VCXO Gain (K
Setting the RPV, RV, FV and SV Divider Values
As shown in the loop bandwidth and damping factor
equations on page 6, or by using the filter response software
available from IDT, increasing FV or SV decreases both
bandwidth and damping factor. Many applications require
that SV = 1. In these cases, one way to decrease loop
bandwidth is to increase the value of FV, which is
accompanied by an increase in the value of RPV and/or RV
Example Loop Filter Component Value
IDT® VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Frequency
19.44 MHz
MK2069-04
VCXO-BASED UNIVERSAL CLOCK TRANSLATOR
Detector
Phase
8 kHz
8 kHz
8 kHz
Notes:
1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244-CORE to satisfy wander
transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer
such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK
in the VCXO PLL
22.368
(MHz)
19.44
19.44
19.44
Freq
Xtal
O
) vs. XTAL Frequency
Div
SV
1
1
1
1
22.368 2796 1 M
VCLK
(MHz)
19.44 2430 1 M
19.44 2430 1 M
19.44
128
Div
FV
6 0 0 0
5 0 0 0
4 0 0 0
3 0 0 0
2 0 0 0
1 0 0 0
R
1 M
SET
560 k
560 k
680 k
27 k
R
1 0
C ry s ta l F re q u e n c y , M H z
S
0.1 F 4.7 nF 27 Hz
1 F
1 F
1 F
C
1 5
S
8
to maintain the same PLL frequency multiplication ratio.
However, the phase detector frequency, F
be considered. F
by the value of the RPV x RV. F
20x the loop bandwidth to prevent loop modulation (phase
noise) by the phase detector frequency. The phase detector
jitter tolerance limit (use 0.4UI) and input phase noise
frequency aliasing should be considerations as well.
4.7 nF 22 Hz
4.7 nF 20 Hz
47 nF
2 0
C
P
(-3dB)
25 Hz
Loop
2 5
BW
Damp.
Loop
3 0
0.85
4.0
1.4
4.5
PD
is equal to the input frequency divided
0.15dB at 1Hz
0.12dB at 1Hz
1.2dB at 6Hz
1.8dB at 8Hz
Passband
Peaking
PD
VCXO AND SYNTHESIZER
should be typically at least
MK2069-04
Note
1
2
3
4
PD
, also needs to
REV J 051310