ICS814252CKI-02LFT IDT, Integrated Device Technology Inc, ICS814252CKI-02LFT Datasheet - Page 9

• Manufacturer Part Number: ICS814252CKI-02LFT
• Description: IC VCXO/FEMTOCLK 2LVDS 32-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™, FemtoClock®r
• Type: Frequency Translator, Jitter Attenuator, Voltage Controlled Crystal Oscillator (VCXO)r

Specifications of ICS814252CKI-02LFT

• Pll: Yes
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Number Of Circuits: 1
• Ratio - Input:output: 3:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 312.5MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN
• Frequency-max: 312.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 814252CKI-02LFT

W
IDT
P
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS814252I-02 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. V
should be individually connected to the power supply plane
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10µF and a 0.01µF bypass capacitor should be con-
nected to each V
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
OWER
ICS814252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
IRING THE
™
/ ICS
™
S
VCXO JITTER ATTENUATOR/MULTIPLIER
UPPLY
D
IFFERENTIAL
DDA
F
ILTERING
pin.
I
NPUT TO
T
ECHNIQUES
F
IGURE
Single Ended Clock Input
DD
A
, V
CCEPT
2. S
A
DDX
PPLICATION
, V
INGLE
S
DDA
INGLE
, and V
E
C1
0.1u
NDED
V_REF
DD
/2 is
E
DDO
S
NDED
IGNAL
9
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
D
EVELS
1K
R1
1K
R2
RIVING
VDD
nCLKx
D
CLKx
IFFERENTIAL
F
IGURE
1. P
V
V
V
I
DDX
DDA
NPUT
ICS814252CKI-02 REV. A OCTOBER 5, 2007
DD
OWER
.01µF
.01µF
DD
= 3.3V, V_REF should be 1.25V
S
UPPLY
.01µF
10Ω
10µF
3.3V
F
ILTERING
10Ω
10µF
PRELIMINARY