LMX2541SQ2060E/NOPB National Semiconductor, LMX2541SQ2060E/NOPB Datasheet - Page 56

• Manufacturer Part Number: LMX2541SQ2060E/NOPB
• Description: IC PLL FREQ SYNTH W/VCO 36LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Clock/Frequency Synthesizer (RF)r

Specifications of LMX2541SQ2060E/NOPB

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: No/No
• Frequency - Max: 2.24GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 36-LLP
• Frequency-max: 2.24GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMX2541SQ2060E

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For example, consider the LMX2541SQ3320E changing from
3600 to 3400 with an OSCin frequency of 100 MHz. In this
case, ΔF = 200 (direction of frequency change does not mat-
ter), f
circuitry is run at a clock speed of CLK = 100 MHz / 4 = 25
MHz. When this values are substituted in the formula, the re-
sulting lock time is 218 μs. After this time, the VCO will be
within about 10 MHz of the final frequency and this final fre-
quency error will settle out in an analog fashion. This final
frequency error can be slightly different depending on which
option of the LMX2541 is being used.
3.11 DIGITAL FSK MODE
The LMX2541 supports 2-level digital frequency shift keying
(FSK) modulation. The bit rate is limited by the loop bandwidth
OSCin
= 100 MHz, and OSC_FREQ=100. The calibration
56
of the PLL loop. As a general rule of thumb, it is desirable to
have the loop bandwidth at least twice the bit rate. This is
achieved by changing the N counter rapidly between two
states. The fractional numerator and denominator are restrict-
ed to a length of 12 bits. The 12 LSB’s of the numerator and
denominator set the center frequency, Fcenter, and the 10
MSB’s of the numerator set the frequency deviation, Fdev.
The LMX2541 has the ability to switch between two different
numerator values based on the voltage at the DATA pin.
When DATA is low, the output frequency will be Fcenter –
Fdev and when the DATA pin is high the output frequency will
be Fcenter + Fdev. A limitation of the FSK mode is the fre-
quency deviation can not cause the N counter to cross integer
boundaries. When using FSK mode, the FDM bit needs to be
set to zero.