NBC12439FAG ON Semiconductor, NBC12439FAG Datasheet
NBC12439FAG
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NBC12439FAG Summary of contents
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NBC12439, NBC12439A 3.3V/5V Programmable PLL Synthesized Clock Generator 50 MHz to 800 MHz Description The NBC12439 and NBC12439A are general purpose, PLL based synthesized clock sources. The VCO will operate over a frequency range of 400 MHz to 800 MHz. The ...
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F REF XTAL_SEL 3 FREF_EXT 7−BIT XTAL1 COUNTER 10−20MHz OSC 5 XTAL2 S_LOAD 7 P_LOAD 27 S_DATA 26 S_CLOCK Table 1. Output Division N [1:0] Output Division ...
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S_CLOCK 26 S_DATA 27 S_LOAD 28 PLL_V 1 CC PWR_DOWN 2 FREF_EXT 3 XTAL1 Figure 2. 28−Lead PLCC (Top View S_CLOCK 1 S_DATA 2 S_LOAD 3 PLL_V ...
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The following gives a brief description of the functionality of the NBC12439 and NBC12349A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pull−up or pulldown resistors. The PECL outputs are capable of driving two series ...
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Table 4. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. ...
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Table 6. DC CHARACTERISTICS (V Symbol V Input HIGH Voltage IH LVCMOS/ LVTTL V Input LOW Voltage IL LVCMOS/ LVTTL I Input Current IN V Output HIGH Voltage OH V Output LOW Voltage OL V Output HIGH Voltage OH PECL ...
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Table 8. AC CHARACTERISTICS (V (NBC12439A)) (Note 7) Symbol Characteristic F Input Frequency IN F Output Frequency OUT t Maximum PLL Lock Time LOCK t Period Jitter (RMS) jitter(pd) t Cycle−to−Cycle Jitter (Peak−to−Peak) jitter(cyc−cyc) t Setup Time s t Hold ...
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The internal oscillator uses the external quartz crystal as the basis of its frequency reference. The output of the reference oscillator is divided by 2 before being sent to the phase detector. With a 16 MHz crystal, this provides a ...
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Programming the NBC12439 and NBC12439A is accomplished by properly configuring the internal dividers to produce the desired frequency at the outputs. The output frequency can by represented by this formula FREF_EXT B 2) OUT XTAL This ...
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Table 11. Frequency Operating Range Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á Á VCO Frequency (MHz) Range for a Crystal Frequency (MHz) of: Á ...
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Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set ...
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Using the On−Board Crystal Oscillator The NBC12439 and NBC12439A feature a fully integrated on−board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. ...
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The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL ...
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JEDEC specification is 1000 cycles. See Figure 11 JITTER(cycle−cycle) 1 Figure 11. Cycle−to−Cycle Jitter Random Peak−to−Peak Jitter is the difference between the highest and lowest acquired value and is ...
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400 500 600 VCO FREQUENCY (MHz) Figure 13. Cycle−to−Cycle RMS Jitter vs. VCO Frequency 700 800 ...
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S_DATA S_CLOCK t SET−UP Figure 15. Setup and Hold S_DATA t S_LOAD SET−UP Figure 16. Setup and Hold M[6:0] N[1:0] P_ LOAD t SET−UP Figure 17. Setup and Hold F OUT F OUT Pulse Width Figure 18. Output Duty Cycle ...
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... F Driver Device F Figure 19. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NBC12439FA NBC12439FAG NBC12439FAR2 NBC12439FAR2G NBC12439FN NBC12439FNG NBC12439FNR2 NBC12439FNR2G NBC12439AFA NBC12439AFAG NBC12439AFAR2 NBC12439AFAR2G NBC12439AFN NBC12439AFNG NBC12439AFNR2 NBC12439AFNR2G NBC12439AMNG NBC12439AMNR4G † ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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0.010 (0.250 NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...
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−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...
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... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...