ADF4107BCP-REEL Analog Devices Inc, ADF4107BCP-REEL Datasheet - Page 6
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ADF4107BCP-REEL
Manufacturer Part Number
ADF4107BCP-REEL
Description
IC PLL FREQ SYNTHESIZER 20-LFCSP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF)r
Datasheet
1.ADF4107BRUZ.pdf
(20 pages)
Specifications of ADF4107BCP-REEL
Rohs Status
RoHS non-compliant
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
2:1
Differential - Input:output
Yes/No
Frequency - Max
7GHz
Divider/multiplier
No/No
Voltage - Supply
2.7 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-LFCSP
Frequency-max
7GHz
ADF4107
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin No.
LFCSP
19
20
1
2, 3
4
5
6, 7
8
9, 10
11
12
13
14
15
16, 17
18
NOTES:
1. TRANSISTOR COUNT 6425 (CMOS),
CPGND
303 (BIPOLAR).
AGND
RF
RF
REF
AV
Figure 3. Pin Configuration, TSSOP
R
SET
IN
IN
Mnemonic
R
CP
CPGND
AGND
RF
RF
AV
REF
DGND
CE
CLK
DATA
LE
MUXOUT
DV
V
CP
DD
IN
B
A
SET
P
IN
IN
DD
DD
IN
1
2
3
4
5
6
7
8
B
A
(Not to Scale)
ADF4107
TOP VIEW
Description
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
so, with R
Charge Pump Output. When enabled, this pin provides ±I
the external VCO.
Charge Pump Ground. This is the ground return path for the charge pump.
Analog Ground. This is the ground return path of the prescaler.
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small
bypass capacitor, typically 100 pF. See Figure 18.
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
Analog Power Supply. This voltage may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator or it can
be ac-coupled.
Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
state mode. Taking the pin high powers up the device, depending on the status of the power-down bit, F2.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches, the latch being selected using the control bits.
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
Charge Pump Power Supply. This voltage should be greater than or equal to V
can be set to 5 V and used to drive a VCO with a tuning range of up to 5 V.
16
15
14
13
12
11
10
9
I
CP
V
DV
MUXOUT
LE
DATA
CLK
CE
DGND
P
MAX
DD
SET
=
= 5.1 kΩ, I
R
25
SET
5 .
CP MAX
= 5 mA.
Rev. A | Page 6 of 20
SET
pin is 0.66 V. The relationship between I
CPGND 1
NOTES:
1. TRANSISTOR COUNT 6425 (CMOS),
AGND 2
AGND 3
RF
RF
303 (BIPOLAR).
CP
DD
IN
IN
Figure 4. Pin Configuration, LFCSP
to the external loop filter, which in turn drives
B 4
A 5
must be the same value as AV
DD
ADF4107
TOP VIEW
DD
must be the same value as DV
PIN 1
INDICATOR
/2 and a dc equivalent input
DD
. In systems where V
CP
and R
15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE
SET
is
DD
.
DD
is 3 V, it
DD
.