ADF4218LBRU-REEL7 Analog Devices Inc, ADF4218LBRU-REEL7 Datasheet

IC PLL FREQ SYNTHESIZER 20-TSSOP

ADF4218LBRU-REEL7

Manufacturer Part Number
ADF4218LBRU-REEL7
Description
IC PLL FREQ SYNTHESIZER 20-TSSOP
Manufacturer
Analog Devices Inc
Type
Clock/Frequency Synthesizer (RF/IF)r
Datasheet
1.ADF4218LBRUZ-REEL.pdf (24 pages)

Specifications of ADF4218LBRU-REEL7

Rohs Status
RoHS non-compliant
Pll
Yes
Input
CMOS
Output
Clock
Number Of Circuits
1
Ratio - Input:output
3:1
Differential - Input:output
Yes/No
Frequency - Max
3GHz
Divider/multiplier
Yes/No
Voltage - Supply
2.6 V ~ 3.3 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
3GHz
a
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FEATURES
Total I
Bandwidth/RF 3.0 GHz
2.6 V to 3.3 V Power Supply
1.8 V Logic Compatibility
Separate V
Selectable Dual Modulus Prescaler
Selectable Charge Pump Currents
Charge Pump Current Matching of 1%
3-Wire Serial Interface
Power-Down Mode
APPLICATIONS
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA)
Wireless LANs
Communications Test Equipment
Cable TV Tuners (CATV)
ADF4217L/ADF4218L, IF 1.1 GHz
ADF4219L, IF 1.0 GHz
DD
: 7.1 mA
P
Allows Extended Tuning Voltage
ADF4217L
ADF4218L
CLOCK
REF
RF
RF
ONLY
IF
DATA
IF
IN
IN
IN
IN
LE
IN
A
A
B
B
FEATURES IN ( ) REFER TO ADF4219L
NC = NO CONNECT
BUFFER
REGISTER
N = BP + A
22-BIT
N = BP + A
DATA
PRESCALER
PRESCALER
RF
IF
SDOUT
ADF4219L ONLY
FUNCTIONAL BLOCK DIAGRAM
NC
11(13)-BIT RF
11(13)-BIT IF
B COUNTER
A COUNTER
A COUNTER
B COUNTER
6(5)-BIT RF
6(5)-BIT IF
V
14(15)-BIT IF
R COUNTER
14(15)-BIT RF
DD
R COUNTER
1
ADF4217L/ADF4218L/ADF4219L
DGND
V
DD
GENERAL DESCRIPTION
The ADF4217L/ADF4218L/ADF4219L are low power dual
frequency synthesizers that can be used to implement local
oscillators in the up-conversion and down-conversion sections
of wireless receivers and transmitters. They can provide the LO
for both the RF and IF sections. They consist of a low noise
digital PFD (phase frequency detector), a precision charge pump, a
programmable reference divider, programmable A and B counters,
and a dual modulus prescaler (P/P + 1). The A and B counters,
in conjunction with the dual modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R Counter) allows selectable REFIN fre-
quencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizers are used with an
external loop filter and VCOs (voltage controlled oscillators).
Control of all the on-chip registers is via a simple 3-wire interface
with 1.8 V compatibility. The devices operate with a power supply
ranging from 2.6 V to 3.3 V and can be powered down when
not in use.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
2
RF
V
P
AGND
1
COMPARATOR
COMPARATOR
RF
V
PHASE
PHASE
P
2
Frequency Synthesizers
DGND
DETECT
DETECT
LOCK
LOCK
RF
IF
IF
© 2003 Analog Devices, Inc. All rights reserved.
AGND
ADF4217L/
ADF4218L/
ADF4219L
CHARGE
CHARGE
OUTPUT
PUMP
PUMP
MUX
IF
Dual Low Power
CP
MUXOUT
CP
IF
RF
www.analog.com

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ADF4218LBRU-REEL7 Summary of contents

Page 1

FEATURES Total Bandwidth/RF 3.0 GHz ADF4217L/ADF4218L, IF 1.1 GHz ADF4219L, IF 1.0 GHz 2 3.3 V Power Supply 1.8 V Logic Compatibility Separate V Allows Extended Tuning Voltage P Selectable Dual Modulus ...

Page 2

ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS ( 2 3 Parameter RF CHARACTERISTICS RF Input Frequency ( ADF4217L, ADF4218L ADF4217L, ADF4218L ADF4219L RF Input Sensitivity ...

Page 3

Parameter 6 NOISE CHARACTERISTICS 7 RF Phase Noise Floor 7 IF Phase Noise Floor 8 Phase Noise Performance Spurious Signals NOTES 1 Operating temperature ...

Page 4

ADF4217L/ADF4218L/ADF4219L 1, 2 ABSOLUTE MAXIMUM RATINGS ( T = 25°C, unless otherwise noted GND . . . . . . . . . . . . . . . . . . . . . ...

Page 5

TSSOP DGND 4 RF ADF4217L ADF4218L AGND 7 RF REF 8 IN DGND 9 IF MUXOUT 10 CHIP SCALE 24 23 ...

Page 6

ADF4217L/ADF4218L/ADF4219L Mnemonic Function V 1 Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as DD close as possible to this pin. V potential Power Supply ...

Page 7

Typical Performance Characteristics– 0 –5 –10 –15 –20 – –30 –35 –40 0 0.5 1.0 1.5 2.0 RF INPUT FREQUENCY – GHz TPC 1. Input Sensitivity, RF Input 0 –5 –10 –15 –20 –25 –30 –35 –40 0.1 ...

Page 8

ADF4217L/ADF4218L/ADF4219L 3V, V REFERENCE DD –10 LEVEL = –4.2dBm I = 4.0mA CP PFD FREQUENCY = 200kHz –20 LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10kHz –30 VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS –40 AVERAGES ...

Page 9

CIRCUIT DESCRIPTION Reference Input Section The reference input stage is shown in Figure 2. SW1 and SW2 are normally closed switches; SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures ...

Page 10

ADF4217L/ADF4218L/ADF4219L The A and B counters, in conjunction with the dual modulus prescaler, make it possible to generate output frequencies that are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: ...

Page 11

Table II. ADF4217L/ADF4218L Family Latch Summary DB21 DB20 DB19 DB18 DB17 DB16 DB21 DB20 DB19 DB18 DB17 DB16 P7 P6 B11 B10 B9 B8 DB21 DB20 DB19 DB18 DB17 DB16 P12 P11 P10 P13 P9 ...

Page 12

ADF4217L/ADF4218L/ADF4219L DB21 DB20 DB19 DB18 DB17 DB16 R15 DB21 DB20 DB19 DB18 DB17 DB16 P7 P6 B13 B12 B11 B10 DB21 DB20 DB19 DB18 DB17 DB16 P13 P12 P11 P10 P9 R15 DB21 DB20 DB19 ...

Page 13

Table IV. ADF4217L/ADF4218L/ADF4219L IF Reference Counter Latch Map DB21 DB20 DB19 DB18 DB17 DB16 R15 P1 PD POLARITY 0 NEGATIVE 1 POSITIVE 1.0mA 1 4.0mA CHARGE PUMP P2 OUTPUT 0 NORMAL ...

Page 14

ADF4217L/ADF4218L/ADF4219L Table V. ADF4217L/ADF4218L IF AB Counter Latch Map DB21 DB20 DB19 DB18 DB17 DB16 P7 P6 B11 B10 B9 B8 B11 B10 ...

Page 15

DB21 DB20 DB19 DB18 DB17 DB16 P7 P6 B13 B12 B11 B10 B13 B12 B11 ...

Page 16

ADF4217L/ADF4218L/ADF4219L DB21 DB20 DB19 DB18 DB17 DB16 P12 P11 P10 P13 P9 R15 P9 PD POLARITY 0 NEGATIVE 1 POSITIVE I P13 CP 0 1.0mA 1 4.0mA CHARGE PUMP P10 OUTPUT 0 NORMAL 1 THREE-STATE P4 P12 P11 FROM RF ...

Page 17

Table VIII. ADF4217L/ADF4218L RF AB Counter Latch Map DB21 DB20 DB19 DB18 DB17 DB16 P16 P14 B11 B10 B9 B8 B11 B10 ...

Page 18

ADF4217L/ADF4218L/ADF4219L DB21 DB20 DB19 DB18 DB17 DB16 P16 P14 B13 B12 B11 B10 B13 B12 B11 ...

Page 19

PROGRAM MODES Tables IV and VII show how to set up the program modes in the ADF4217L family. The following should be noted and RF Analog Lock Detect indicate when the PLL is in lock. When the loop ...

Page 20

ADF4217L/ADF4218L/ADF4219L RF Program Modes Tables IV and VII show how to set up the RF program modes. RF Charge Pump Currents P13 sets the RF charge pump current. With P13 set to “0,” I 1.0 mA. With P13 set to ...

Page 21

IF OUT 100pF 18 100pF VCO190-200T 18 450pF 100pF 51 10MHz TCXO DECOUPLING CAPACITORS (22 F/10pF THE TCXO AND THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY. CC Figure ...

Page 22

ADF4217L/ADF4218L/ADF4219L 20-Lead Thin Shrink Small Outline Package [TSSOP] PIN 1 0.15 0.05 COPLANARITY 0.10 4.50 BSC TOP VIEW PIN 1 INDEX AREA 1 24 BOTTOM VIEW OUTLINE DIMENSIONS (RU-20) Dimensions shown in millimeters 6.60 6.50 6. 4.50 4.40 ...

Page 23

Revision History Location 5/03—Data Sheet changed from REV REV. C. Change to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 24

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