ADF4360-1BCPRL Analog Devices Inc, ADF4360-1BCPRL Datasheet - Page 11

• Manufacturer Part Number: ADF4360-1BCPRL
• Description: IC INTEG SYNTH/VCO 24-LFCSP T/R
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-1BCPRL

• Rohs Status: RoHS non-compliant
• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 2.45GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 2.45GHz
• For Use With: EVAL-ADF4360-1EBZ1 - BOARD EVALUATION FOR ADF4360-1

After band select, normal PLL action resumes. The nominal value
of K
selected (by programming DIV2 [DB22], high in the N counter
latch). The ADF4360 family contains linearization circuitry to
minimize any variation of the product of I
The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.
OUTPUT STAGE
The RF
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −13 dBm, −10.5 dBm,
−8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to V
and ac coupling into a 50 Ω load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the Output Matching section).
V
is 57 MHz/V or 28 MHZ/V if divide-by-2 operation has been
OUT
A and RF
OUT
B pins of the ADF4360 family are con-
CP
and K
V
.
DD
Rev. B | Page 11 of 24
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
mute-till-lock detect (MTLD) bit in the control latch.
VCO
Figure 15. Output Stage ADF4360-1
DIVIDE BY 2
BUFFER/
DD
RF
.
OUT
A
RF
OUT
ADF4360-1
B