AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 72

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
Reg.
Addr.
(Hex)
0x197
0x198
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
0x199
0x19A
0x19B
0x19C
0x19D
0x19E
Bits
4
[3:0]
1
0
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
5
4
3
2
1
0
0
[7:4]
[3:0]
Low Cycles Divider 2.2
Low Cycles Divider 3.1
Name
Divider 1 start high
Divider 1 phase offset
Divider 1 direct to output
Divider 1 DCCOFF
Name
Low Cycles Divider 2.1
High Cycles Divider 2.1
Phase Offset Divider 2.2
Phase Offset Divider 2.1
High Cycles Divider 2.2
Bypass Divider 2.2
Bypass Divider 2.1
Divider 2 nosync
Divider 2 force high
Start High Divider 2.2
Start High Divider 2.1
Divider 2 DCCOFF
High Cycles Divider 3.1
Description
Selects clock output to start high or start low.
0: start low (default).
1: start high.
Phase offset (default = 0x0).
Connect OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Description
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass (and power-down) 2.2 divider logic, route clock to 2.2 output.
0: do not bypass (default).
1: bypass.
Bypass (and power-down) 2.1 divider logic, route clock to 2.1 output.
0: do not bypass (default).
1: bypass.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force Divider 2 output high. Requires that nosync also be set.
0: force low (default).
1: force high.
Divider 2.2 start high/low.
0: start low (default).
1: start high.
Divider 2.1 start high/low.
0: start low (default).
1: start high.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Rev. B | Page 72 of 80