SY89531LHC Micrel Inc, SY89531LHC Datasheet - Page 3

• Manufacturer Part Number: SY89531LHC
• Description: IC SYNTHESIZR LVPECL/HSTL 64TQFP
• Manufacturer: Micrel Inc
• Series: Precision Edge®r
• Type: Clock/Frequency Synthesizerr

Specifications of SY89531LHC

• Pll: Yes
• Input: Crystal
• Output: HSTL, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:13
• Differential - Input:output: No/Yes
• Frequency - Max: 500MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 1.6 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP Exposed Pad, 64-eTQFP, 64-HTQFP, 64-VQFP
• Frequency-max: 500MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Micrel, Inc.
Power
Configuration
Input/Output
M9999-010808
[e-mail] or [phone]
PIN DESCRIPTION
(exposed pad)
51, 52, 53, 54
17, 18, 19, 20
Pin Number
9, 25, 63, 29
Pin Number
Pin Number
13,14,15,16
30, 31, 50
22, 23, 24
26, 27, 28
56, 57, 58
60, 61
1, 2, 3
10, 11
32–49
5, 6
62
55
21
59
12
64
4
7
8
XTAL2, XTAL1
LOOP FILTER
FSEL_C (2:0)
FSEL_B (2:0)
FSEL_A (2:0)
OUT_SYNC
QA1 to QA0
QB8 to QB0
QC1 to QC0
/EXT_VCO,
LOOP REF
Pin Name
Pin Name
VCO_SEL
Pin Name
VBB_REF
EXT_VCO
V
V
V
V
M (3:0)
CC_Logic
V
GND
CCO
CCO
CCO
NC
NC
CCA
C
A
B
Pin Function
Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally
connected on the die, and must be connected together on the PCB.
Power for Output Drivers: Connect all V
pins to 1.8V supply.
Ground: Exposed pad must be soldered to a ground plane.
Pin Function
LVTTL/CMOS Compatible Input: Selects between internal or external VCO. For
external VCO, leave floating. Default condition is logic HIGH. Internal 25k pull-up.
When tied LOW, internal VCO is selected.
Analog Input/Output: Provides the reference voltage for PLL loop filter.
Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter
Considerations” for loop filter values.
LVTTL/CMOS Compatible Input: Used to change the PLL feedback divider. Internal 25k
pull-up. M0 = LSB. Default is logic HIGH. See “Feedback Divide Select” table.
LVTTL/CMOS Compatible Input: Bank C post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_C0 = LSB.
LVTTL/CMOS Compatible Input: Bank B post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_B0 = LSB.
LVTTL/CMOS Compatible Input: Bank A post divide select. Internal 25k pull-up.
Default is logic HIGH. See “Post-Divide Frequency Select” table. FSEL_A0 = LSB.
Banks A, B, C Output Synchronous Control: (LVTTL/CMOS compatible). Internal 25k
pull-up. After any bank has been programmed, toggle with a HIGH-LOW-HIGH
pulse to resynchronize all output banks.
Pin Function
No Connect: Leave floating.
Crystal Input. Directly connect a series resonant crystal across inputs.
Reference Output Voltage. Used for single-ended input. Maximum sink/source
current = 0.5mA.
Differential “Any In” Compatible Input Pair. Allows for external VCO connection. The “Any
In” input structure accepts many popular logic types. See “Input Interface for ExtVCO Pins”
section for interface diagrams. Can leave unconnected if using internal VCO.
Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A
(0:2). Terminate outputs with 50 to V
Recommendations” section.
Bank B Output Drivers: Differential HSTL outputs. See “Output Termination Recommendations”
section. Output frequency is controlled by FSEL_B (0:2).
Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2).
Terminate outputs with 50 to V
No Connect: Leave floating.
3
CC
–2V. See “Output Termination Recommendations” section.
CC
CCO
–2V. See “Output Termination
A and V
CCO
C pins to 3.3V supply and V
Precision Edge
SY89531L
CCO
B
®