CY28411ZXC-1 Cypress Semiconductor Corp, CY28411ZXC-1 Datasheet - Page 10

IC CLOCK GEN ALVISO 56-TSSOP

CY28411ZXC-1

Manufacturer Part Number
CY28411ZXC-1
Description
IC CLOCK GEN ALVISO 56-TSSOP
Manufacturer
Cypress Semiconductor Corp
Type
Fanout Distribution, Spread Spectrum Clock Generatorr
Datasheet

Specifications of CY28411ZXC-1

Pll
Yes
Input
LVTTL, Crystal
Output
Clock
Number Of Circuits
1
Ratio - Input:output
7:20
Differential - Input:output
No/Yes
Frequency - Max
266MHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
56-TSSOP II
Frequency-max
100MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY28411ZXC-1
Manufacturer:
CY
Quantity:
42
Part Number:
CY28411ZXC-1
Manufacturer:
CY
Quantity:
880
Document #: 38-07694 Rev. *B
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPU_STOP#
CPUC Internal
CPUT Internal
CPU_STP#
CPU_STP#
DOT96C
DOT96T
CPUT
CPUC
CPUT
CPUC
PD
Figure 7. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 6. CPU_STP# Deassertion Waveform
Figure 5. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#,10nS>200mV
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z.
CY28411-1
1.8mS
Page 10 of 19

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