CY28RS400ZXC Cypress Semiconductor Corp, CY28RS400ZXC Datasheet - Page 13

• Manufacturer Part Number: CY28RS400ZXC
• Description: IC CLOCK GENERATOR 56-TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Clock Generatorr

Specifications of CY28RS400ZXC

• Frequency - Max: 100MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP II
• Frequency-max: 100MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output: -
• Input: -

Document #: 38-07637 Rev. *B
Absolute Maximum Conditions
DC Electrical Specifications
AC Electrical Specifications
UL-94
MSL
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
Crystal
T
VDD_CPU,
VDD_SRC,
Parameter
Parameter
VDD_REF,
V
VDD_PCI,
V
Parameter
DC
VDD_48,
ESD
IHSMBUS
ILSMBUS
V
V
V
C
IPD
V
IPD
V
V
V
Ø
Ø
V
IDD
V
IH_FS
V
I
C
IL_FS
V
L
DDA
T
T
T
OUT
I
OZ
XIH
DD
OH
XIL
OL
IL
IN
IN
JC
JA
IH
A
IL
IN
S
HBM
J
D
T
Core Supply Voltage
Analog Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
ESD Protection (Human Body Model)
Dissipation, Junction to Case
Dissipation, Junction to Ambient
Flammability Rating
Moisture Sensitivity Level
3.3V Operating Voltage
FS_A,FS_B and FS_C Input Low Voltage
FS_A,FS_B and FS_C Input Low Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Leakage Current
Output Low Voltage
Output High Voltage
High-Impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
Xin High Voltage
Xin Low Voltage
Dynamic Supply Current
Power Down Supply Current
Power Down Supply Current
XIN Duty Cycle
Description
Description
Description
3.3V ± 5%
SDATA, SCLK
SDATA, SCLK
VDD
except Pull-ups or Pull downs 0<V
I
I
At max load and frequency
PD asserted, Outputs driven
PD asserted, Outputs Hi-Z
OL
OH
= 1 mA
Relative to VSS
Non Functional
Functional
Functional
MIL-STD-883, Method 3015
Mil-Spec 883E Method 1012.1
JEDEC (JESD 51)
At 1/8 in.
= 1 mA
The device will operate reliably with
input duty cycles up to 30/70 but the
REF clock duty cycle will not be
within specification
Condition
Condition
Condition
IN
<V
DD
V
V
0.7*V
SS
SS
2000
Min.
3.135
–0.5
–0.5
–0.5
–65
Min.
–10
0.7
2.2
2.0
2.4
0
–
–
–
–5
Min.
47.5
–
–
3
3
–
0
–
–
–
– 0.3
– 0.3
DD
CY28RS400
V–0
V
1
V
V
DD
Max.
+150
0.3*V
150
DD
4.6
4.6
DD
70
20
60
3.465
Max.
Page 13 of 19
–
0.35
V
450
+0.5
1.0
0.8
0.4
10
75
Max.
52.5
DD
–
5
5
5
7
2
-
+ 0.5
+ 0.3
DD
°C/W
°C/W
Unit
V
Unit
°C
°C
°C
mA
mA
mA
mA
nH
Unit
V
V
DC
V
uA
pF
pF
V
V
V
V
V
V
V
V
V
V
V
%
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