CY29773AXI Cypress Semiconductor Corp, CY29773AXI Datasheet - Page 9

• Manufacturer Part Number: CY29773AXI
• Description: IC CLK ZDB 14OUT 125MHZ 52TQFP
• Manufacturer: Cypress Semiconductor Corp
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr
• Series: Spread Aware™r

Specifications of CY29773AXI

• Number Of Circuits: 1
• Package / Case: 52-TQFP
• Pll: Yes with Bypass
• Input: LVCMOS, LVPECL
• Output: LVCMOS
• Ratio - Input:output: 4:12
• Differential - Input:output: No/No
• Frequency - Max: 200MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 200MHz
• Maximum Input Frequency: 125 MHz
• Minimum Input Frequency: 5 MHz
• Output Frequency Range: 8.3 MHz to 200 MHz
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 2.375 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document #: 38-07573 Rev. *A
Power Management
The individual output enable/freeze control of the CY29773
allows the user to implement unique power management
schemes into the design. The outputs are stopped in the logic
‘0’ state when the freeze control bits are activated. The serial
input register contains one programmable freeze enable bit for
12 of the 14 output clocks. The QC0 and FB_OUT outputs can
not be frozen with the serial port, this avoids any potential lock
up situation should an error occur in the loading of the serial
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
VCO
QC
QC
QC
QC
QC
QC
QC
QA
QA
QA
QA
QA
QA
QA
Figure 1.
1:1 Mode
2:1 Mode
3:1 Mode
3:2 Mode
4:1 Mode
4:3 Mode
6:1 Mode
data. An output is frozen when a logic ‘0’ is programmed and
enabled when a logic ‘1’ is written. The enabling and freezing
of individual outputs is done in such a manner as to eliminate
the possibility of partial “runt” clocks.
The serial input register is programmed through the SDATA
input by writing a logic ‘0’ start bit followed by 12 NRZ freeze
enable bits. The period of each SDATA bit equals the period of
the free running SCLK signal. The SDATA is sampled on the
rising edge of SCLK.
CY29773
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