SI4133G-BM Silicon Laboratories Inc, SI4133G-BM Datasheet
SI4133G-BM
Specifications of SI4133G-BM
Related parts for SI4133G-BM
SI4133G-BM Summary of contents
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... IFLB RFLC 6 19 IFLA GNDR 7 18 RFLB GNDD 8 17 VDDD RFLA 9 16 GNDR GNDD 10 15 GNDR XIN 11 14 PWDN RFOUT 12 13 VDDR AUXOUT Si4133G- GNDR GNDI RFLD 2 20 IFLB RFLC 3 19 IFLA GND GNDR 4 18 GNDD Pad RFLB 5 17 VDDD RFLA ...
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... Si4133G 2 Rev. 1.4 ...
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... RF and IF Outputs (RFOUT and IFOUT Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Powerdown Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Auxiliary Output (AUXOUT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pin Descriptions: Si4133G- Pin Descriptions: Si4133G- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Si4133G Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package Outline: Si4133G- Package Outline: Si4133G- Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Rev. 1.4 Si4133G Page 3 ...
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... Si4133G Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at 3.0 V and an operating temperature of 25 °C unless otherwise stated. ...
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... For signals SCLK, SDATA, SEN, and PWDN. 3. For signal AUXOUT. Symbol Test Condition RF1 and IF Operating PWDN = –500 µ 500 µ Rev. 1.4 Si4133G Min Typ Max Unit — — — — — 1 — µA 0.7 V — — — — 0 –10 — 10 µA –10 — ...
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... Si4133G Table 4. Serial Interface Timing (V = 2 – ° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 SDATA Setup Time to SCLK↑ 2 SDATA Hold Time from SCLK↑ 2 SEN↓ to SCLK↑ Delay Time 2 SCLK↑ ...
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... SCLK SDATA D17 t en1 SEN Figure 2. Serial Interface Timing Diagram First bit c loc ked hold D16 D15 data field Figure 3. Serial Word Format Rev. 1.4 Si4133G A0 t en3 t en2 t w Last bit c loc ked address field 7 ...
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... Si4133G Table 5. RF and IF Synthesizer Characteristics (V = 2 – ° Parameter XIN Input Frequency Reference Amplifier Sensitivity Phase Detector Update Frequency RF1 Center Frequency Range RF2 Center Frequency Range IF VCO Center Frequency Range Tuning Range from f CEN RF1 VCO Pushing RF2 VCO Pushing ...
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... PWDN SEN PDIB = 1 SDATA PDRB = 1 Figure 4. Software Power Management Timing Diagram RF and IF synthesizers settled to within 0.1 ppm frequency error. t pup PWDN PWDN Figure 5. Hardware Power Management Timing Diagram Rev. 1.4 Si4133G t pdn PDIB = 0 PDRB = 0 t pdn 9 ...
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... Si4133G TRACE A: Ch1 FM Gate Time A Offset 800 Hz Real 160 Hz /div -800 Hz Start Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency 10 133.59375 us Stop: 299.21875 us Rev. 1.4 ...
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... Offset Frequency (Hz) Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1 Si4133G 6 11 ...
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... Si4133G −60 −70 −80 −90 −100 −110 −120 −130 −140 2 10 Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency Offset Frequency (Hz) Rev ...
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... Offset Frequency (Hz) Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 550 MHz with 200 kHz Phase Detector Update Frequency Rev. 1 Si4133G 6 13 ...
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... GNDI 20 IFLB 19 IFLA 18 Si4133G-BM GNDD 17 VDDD 16 GNDD 15 XIN µF 0.022 Figure 14. Si4133G-BM Rev. 1.4 µF 0.022 40 nH 560 pF IFOUT Printed Trace Inductor or Chip Inductor µF 0.022 560 pF External Clock PWDN AUXOUT 40 nH 560 pF IFOUT Printed Trace Inductor or Chip Inductor V DD µF ...
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... PLL is active at a time. Because the two VCOs can be set to have widely separated center frequencies, the RF output can be programmed to service different frequency bands, thus the Si4133G is ideal for dual- band cellular handsets. The unique PLL architecture in the Si4133G produces a transient response that is superior in speed to ...
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... PKG (MHz) (pF) (nH) Min Max RF1 947 1720 4.3 2.0 RF2 789 1429 4.8 2.3 IF 526 952 6.5 2.1 Table 7. Si4133G-BM VCO Characteristics VCO F Range C L CEN NOM PKG (MHz) (pF) (nH) Min Max RF1 947 1720 4.3 1.5 RF2 789 1429 4 ...
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... Si4133G executes the self-tuning algorithm. From then on the PLL controls the output frequency. Because of the unique architecture of the Si4133G PLLs, the time required to settle the output frequency to 0.1 ppm error is approximately 21 update periods. Total time after powerup or a change in ...
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... Table 9 summarizes the powerdown functionality. The Si4133G can be powered down by taking the PWDN pin low or by setting bits in the Powerdown register (Register 1). When the PWDN pin is low, the Si4133G will be powered down regardless of the Powerdown L register settings. When the PWDN pin is high, power ...
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... Table 9. Powerdown Configuration PWDN Pin AUTOPDB PDIB x x PWDN = PWDN = Rev. 1.4 Si4133G RF PDRB IF Circuitry Circuitry x OFF OFF 0 OFF OFF 1 OFF OFF ...
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... Si4133G Control Registers Register Name Bit Bit Main 0 0 Configuration 1 Reserved 2 Powerdown RF1 N-Divider 4 RF2 N-Divider N-Divider Reserved . . . 15 Reserved Note: Registers 1 and 6–15 are reserved. Writes to these registers can result in unpredictable behavior. Registers not listed here are reserved and should not be written. ...
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... Output Power-Level Settings for IF Synthesizer Circuit. < 500 Ω —normal power mode LOAD ≥ 500 Ω —low power mode LOAD Program to zero. Auto Powerdown 0 = Software powerdown is controlled by Register Equivalent to setting all bits in Register Program to zero. Program to one . Program to zero. Rev. 1.4 Si4133G LPWR AUTO PDB Function ...
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... Si4133G Register 2. Powerdown Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Register 3. RF1 N-Divider Address Field (A[3:0]) = 0011 Bit D17 D16 D15 D14 D13 D12 D11 D10 Name Bit ...
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... Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name 0 0 Bit Name 17:16 Reserved 15:0 N [15: [16:0] RF2 Function [15:0] IF Function Program to zero. N-Divider for IF Synthesizer. Register reserved for Si4113G. Writes to this register can result in unpredictable behavior. Rev. 1.4 Si4133G ...
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... Si4133G Pin Descriptions: Si4133G-BT Pin Number Name Description 1 SCLK Serial clock input 2 SDATA Serial data input 3 GNDR Common ground for RF analog circuitry 4 RFLD Pins for inductor connection to RF2 VCO 5 RFLC Pins for inductor connection to RF2 VCO 6 GNDR Common ground for RF analog circuitry ...
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... Table 11. Pin Descriptions for Si4133G Derivatives—TSSOP Pin Number Si4133G-BT Si4123G-BT Si4122G-BT Si4113G-BT 1 SCLK SCLK 2 SDATA SDATA 3 GNDR GNDR 4 RFLD GNDR 5 RFLC GNDR 6 GNDR GNDR 7 RFLB RFLB 8 RFLA RFLA 9 GNDR GNDR 10 GNDR GNDR 11 RFOUT RFOUT 12 VDDR VDDR 13 AUXOUT AUXOUT 14 PWDN PWDN ...
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... Si4133G Pin Descriptions: Si4133G-BM Pin Number Name Description 1 GNDR Common ground for RF analog circuitry 2 RFLD Pins for inductor connection to RF2 VCO 3 RFLC Pins for inductor connection to RF2 VCO 4 GNDR Common ground for RF analog circuitry 5 RFLB Pins for inductor connection to RF1 VCO ...
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... Table 12. Pin Descriptions for Si4133G Derivatives—MLP Pin Number Si4133G-BM Si4123G-BM Si4122G-BM Si4113G-BM 1 GNDR GNDR 2 RFLD GNDR 3 RFLC GNDR 4 GNDR GNDR 5 RFLB RFLB 6 RFLA RFLA 7 GNDR GNDR 8 GNDR GNDR 9 GNDR GNDR 10 RFOUT RFOUT 11 VDDR VDDR 12 AUXOUT AUXOUT 13 PWDN PWDN 14 GNDD GNDD ...
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... Si4133G Ordering Guide Ordering Part Number Si4133G-BT* Si4133G-BM Si4123G-BT* Si4123G-BM Si4122G-BT* Si4122G-BM Si4113G-BT* Si4113G-BM *Note: TSSOP not recommended for new designs. Si4133G Derivative Devices The Si4133G performs both IF and dual-band RF frequency synthesis. The Si4113G, Si4122G, and the Si4123G are derivatives of this device. Table 13 outlines which synthesizers each derivative device features as well as which pins and registers coincide with each synthesizer ...
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... Package Outline: Si4133G-BT Figure 19 illustrates the package details for the Si4133G-BT. Table 14 lists the values for the dimensions shown in the illustration. D γ Figure 19. 24-Pin Thin Shrink Small Outline Package (TSSOP) Table 14. Package Diagram Dimensions Symbol *Note: To guarantee coplanarity ( E H θ Approximate device weight is 115.7 mg. ...
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... Si4133G Package Outline: Si4133G-BM Figure 20 illustrates the package details for the Si4133G-BM. Table 15 lists the values for the dimensions shown in the illustration D TOP VIEW Figure 20. 28-Pin Micro Leadframe Package (MLP E1/2 E θ SECTION "C–C" SCALE: NONE e Table 15. Package Dimensions ...
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... Document Change List Revision 1.3 to Revision 1.4 TSSOP outline updated. Rev. 1.4 Si4133G 31 ...
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... Si4133G Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free:1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...