SI5318-F-BC Silicon Laboratories Inc, SI5318-F-BC Datasheet - Page 22

• Manufacturer Part Number: SI5318-F-BC
• Description: IC MULTIPLIER SONET/SDH 63CBGA
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5318-F-BC

• Package / Case: 63-CBGA
• Pll: Yes
• Input: LVTTL
• Output: LVTTL
• Number Of Circuits: 1
• Ratio - Input:output: 1:1
• Differential - Input:output: Yes/Yes
• Frequency - Max: 173MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -20°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 173MHz
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 336-1180

Si5318
22
*Note: The LVTLL inputs on the Si5318 device have an internal pulldown mechanism that causes these inputs to default to a
Pin #
D1
B4
E1
logic low state if the input is not driven from an external source.
FXDDELAY
Pin Name
CLKIN+
CLKIN–
I/O
I*
I
Table 10. Si5318 Pin Descriptions
200–500 mV
(See Table 2)
Signal Level
AC Coupled
LVTTL
Rev. 1.0
PPD
Fixed Delay Mode.
Set high to disable hitless recovery from digital hold
mode. This configuration is useful in applications that
require a known, or constant, input-to-output phase
relationship.
When this pin is high, hitless switching from digital
hold mode back to a valid clock input is disabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY high, the clock output
changes as necessary to re-establish the initial/
default input-to-output phase relationship that is
established after powerup or reset. The rate of
change is determined by the setting of BWSEL[1:0].
When this pin is low, hitless switching from digital
hold mode back to a valid clock input is enabled.
When switching from digital hold mode to a valid
clock input with FXDDELAY low, the device enables
"phase build out" to absorb the phase difference
between the clock output and the clock input so that
the phase change at the clock output is minimized. In
this case, the input-to-output phase relationship fol-
lowing the transition out of digital hold mode is deter-
mined by the phase relationship at the time that
switching occurs.
Note: FXDDELAY should remain at a static high or static
System Clock Input.
Clock input to the DSPLL circuitry. The frequency of
the CLKIN signal is multiplied by the DSPLL to gen-
erate the CLKOUT clock output. The input-to-output
frequency multiplication factor is set by selecting the
clock input range and the clock output range. The fre-
quency of the CLKIN clock input can be in the 19, 39,
78, or 155 MHz range (nominally 19.44, 38.88,
77.76, or 155.52 MHz) as indicated in Table 3 on
page 7. The clock input frequency is selected using
the INFRQSEL[2:0] pins. The clock output frequency
is selected using the FRQSEL[1:0] pins.
low level during normal operation. Transitions on
this pin are allowed only when the RSTN/CAL pin is
low. FXDDELAY must be set high when DBLBW is
set high.
Description