PI6C3991-2JE Pericom Semiconductor, PI6C3991-2JE Datasheet
PI6C3991-2JE
Specifications of PI6C3991-2JE
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PI6C3991-2JE Summary of contents
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... Description PI6C3991 offers selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize the timing of high-perfor- mance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated trans- ...
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... NOM NOM 2 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer - SuperClock – – – – / and Time Unit Generator NOM when the output connected NOM / when the part is configured for a frequency NOM PI6C3991 ( – – – – – – PS8450C 08/15/02 ...
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... High-Speed, Low-Voltage Programmable Test Mode The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the PI6C3991 to operate as explained briefly above (for testing purposes, any of the three level inputs can have a removable jumper to ground tied LOW through a 100 Ohm resistor ...
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... V and the PLL may require an additional t 5. PI6C3991 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 6. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters. ...
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... Notes: 7. Test measurement levels for the PI6C3991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. 8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. ...
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... REF Divided Vth=1. REF RPWL t RPWH t t ODCV ODCV t SKEWPR t SKEWPR t SKEW0 SKEW0 SKEW2 t t SKEW3,4 SKEW3,4 t SKEW1,3,4 6 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer - SuperClock TTL Input Test Waveform 1ns 1ns 3.0V 2.0V 0. SKEW2 t SKEW3,4 t SKEW2,4 PI6C3991 t JR PS8450C 08/15/02 ...
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... System Clock Figure 2 shows the SuperClock configured as a zero-skew clock buffer. In this mode the PI6C3991 can be used as the basis for a low- skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load ...
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... Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. 8 Skew Clock Buffer - SuperClock REF FB REF FS 4F0 4Q0 4F1 4Q1 3F0 3Q0 3F1 3Q1 2F0 2Q0 2F1 2Q1 1F0 1Q0 1F1 1Q1 TEST PS8450C PI6C3991 40 MHz 20 MHz 80 MHz 08/15/02 ...
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... TEST Figure 7. Multi-Function Clock Driver 9 3.3V High-Speed, Low-Voltage Programmable Skew Clock Buffer - SuperClock LOAD MHz Inverted LOAD MHz LOAD 80 MHz Z Zero Skew 0 80 MHz Skewed LOAD –3.125ns (– PI6C3991 PS8450C 08/15/02 ...
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... TEST Figure 8 shows the PI6C3991 connected in series to construct a zero skew clock distribution tree between boards. Delays of the down stream clock buffers can be programmed to compensate for the wire length (i.e., select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zero- 3 ...
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... Package Diagram - 32-Pin PLCC (J) Ordering Information 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 3.3V High-Speed, Low-Voltage Programmable Pericom Semiconductor Corporation 1 1 Skew Clock Buffer - SuperClock PS8450C PI6C3991 08/15/02 ...