SI5322-B-GM Silicon Laboratories Inc, SI5322-B-GM Datasheet
SI5322-B-GM
Specifications of SI5322-B-GM
Related parts for SI5322-B-GM
SI5322-B-GM Summary of contents
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... VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5322 is ideal for providing clock multiplication in high performance timing applications. Applications ...
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... Si5322 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock Frequency CK OF (CKOUT1, CKOUT2) 3-Level Input Pins Input Mid Current I IMM Input Clocks (CKIN1, CKIN2) ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air www.silabs.com/timing Symbol DIG T JCT T STG Preliminary Rev. 0.5 Si5322 Min Typ Max Unit –40 — — 0.6 TBD ps rms — 0.6 TBD ps rms — ...
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... Si5322 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 MHz 4 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot ...
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... Clock Output 2 Disable/ DBL2_BY Bypass Mode Control 15 kΩ Reset RST Notes: 1. Assumes differential LVEPECL termination (3 clock inputs. 2. Denotes tri-level input pins with states designated as L (ground Assumes manual input clock selection. Figure 2. Si5322 Typical Application Circuit C 1 µ 0.1 µF 3 Ferrite Bead C 0.1 µ ...
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... Si5322 1. Functional Description The Si5322 is a low jitter, precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, SDH STM-16/64 Ethernet, and Fibre Channel. The Si5322 accepts dual clock inputs ranging from 19.44 to 707 MHz and generates two frequency- multiplied clock outputs ranging from 19.44 to 1050 MHz ...
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... Resets all internal logic to a known state. Clock out- LVCMOS puts are tristated during reset. After rising edge of RST sig- nal, the Si5322 will perform an internal self-calibration. This pin has a weak pull-up. Frequency Table Select. Selects SONET/SDH, datacom, or SONET/SDH to datacom frequency table ...
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... Si5322 Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O 4 C2B O 5, 10 8,19, GND GND 20 AUTOSEL I 12 CKIN2 CKIN2– 14 DBL2_BY I 16 CKIN1 CKIN1– 8 Signal Level CKIN2 Loss of Signal. Active high loss-of-signal indicator for CKIN2. Once trig- LVCMOS gered, the alarm will remain active until CKIN2 is validated. ...
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... Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level 21 CS_CA I/O 23 BWSEL1 I 22 BWSEL0 27 FRQSEL3 26 FRQSEL2 I 25 FRQSEL1 24 FRQSEL0 Input Clock Select/Active Clock Indicator. Input: If manual clock selection mode is chosen (AUTOSEL = L), this pin functions as the manual input clock selector. This input is internally deglitched to prevent inadvertent clock switching during changes in the CS input state ...
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... Si5322 Table 3. Si5322 Pin Descriptions (Continued) Pin # Pin Name I/O 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– CKOUT2+ 29 CKOUT1– CKOUT1 — GND PAD GND GND 10 Signal Level Signal Format Select. Three level inputs that select the output signal format (com- mon mode voltage and differential swing) for both CKOUT1 and CKOUT2 ...
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... Ordering Guide Ordering Part Number Si5322-C-GM 36-Lead QFN Package ROHS6, Pb-Free Yes Preliminary Rev. 0.5 Si5322 Temperature Range – °C 11 ...
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... Si5322 4. Package Outline: 36-Pin QFN Figure 3 illustrates the package details for the Si5322. Table 4 lists the values for the dimensions shown in the illustration. Figure 3. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC D2 3 ...
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... Recommended PCB Layout Figure 4. PCB Land Pattern Diagram Preliminary Rev. 0.5 Si5322 13 ...
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... Si5322 Table 5. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0 ...
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... Changed 1.8 V operating range to ±5%. Updated Table 1 on page 2. Updated Table 2 on page 3. Updated Figure 2 on page 5 to add pull-up/pull-down resistors for 3-level inputs. Added figure and table on page 4. Updated 1."Functional Description" on page 6. Clarified 2."Pin Descriptions: Si5322" on page 7. Updated SFOUT values. Preliminary Rev. 0.5 Si5322 15 ...
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... Si5322 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...