SI5326A-B-GM Silicon Laboratories Inc, SI5326A-B-GM Datasheet - Page 8

• Manufacturer Part Number: SI5326A-B-GM
• Description: IC ANY-RATE MULTI/ATTEN 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Clock Multiplierr

Specifications of SI5326A-B-GM

• Package / Case: 36-QFN
• Pll: Yes
• Input: Clock
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.4GHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 1.62 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 1.4GHz
• Mounting Style: SMD/SMT
• Number Of Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5326
8
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map.
5, 10, 32
Pin #
8, 31
11
15
16
17
12
13
18
4
7
6
Pin Name
CKIN1+
CKIN1–
CKIN2+
CKIN2–
RATE0
RATE1
GND
C2B
V
LOL
XB
XA
DD
GND
V
I/O
O
O
DD
I
I
I
I
Signal Level
LVCMOS
LVCMOS
3-Level
Supply
Analog
Supply
Multi
Multi
Confidential Rev. 0.2
CKIN2 Invalid Indicator.
This pin functions as a LOS (and optionally FOS) alarm indicator
for CKIN2 if CK2_BAD_PIN = 1.
0 = CKIN2 present.
1 = LOS (FOS) on CKIN2.
The active polarity can be changed by CK_BAD_POL. If
CK2_BAD_PIN = 0, the pin tristates.
Supply.
The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass
capacitors should be associated with the following Vdd pins:
5
10
32
A 1.0 µF should be placed as close to the device as is practical.
External Crystal or Reference Clock.
External crystal should be connected to these pins to use internal
oscillator based reference. If external reference is used, apply ref-
erence clock to XA input and leave XB pin floating. External refer-
ence must be from a high-quality clock source (TCXO, OCXO).
Frequency of crystal or external clock is set by RATE[1:0] pins.
Ground.
Must be connected to system ground. Minimize the ground path
impedance for optimal performance of this device.
External Crystal or Reference Clock Rate.
Three level inputs that select the type and rate of external crystal
or reference clock to be applied to the XA/XB port.
LM = 38.88 MHz external clocks
MM = 114.285 MHz 3rd OT crystal
HH = converts part to Si5325, and no external crystal or reference
is needed
Clock Input 1.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
Clock Input 2.
Differential input clock. This input can also be driven with a single-
ended signal. Input frequency range is 2 kHz to 710 MHz.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator if the
LOL_PIN register bit is set to 1.
0 = PLL locked.
1 = PLL unlocked.
If LOL_PIN = 0, this pin will tristate. Active polarity is controlled by
the LOL_POL bit. The PLL lock status will always be reflected in
the LOL_INT read only register bit.
0.1 µF
0.1 µF
0.1 µF
Description