SY89297UMG Micrel Inc, SY89297UMG Datasheet - Page 8

• Manufacturer Part Number: SY89297UMG
• Description: IC DELAY LINE 2CH IND MLF44Q-24L
• Manufacturer: Micrel Inc

Specifications of SY89297UMG

• Number Of Taps/steps: *
• Function: *
• Delay To 1st Tap: *
• Tap Increment: *
• Available Total Delays: *
• Number Of Independent Delays: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 24-MLF®, QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3706-5; SY89297UMG

Micrel, Inc.
12. SCLK has to transition L-H a hold time after the SLOAD H-L transition to ensure that the valid data is properly latched before starting to load new
13. This hold time is the minimum time that /EN must remain asserted after a negative going transition of IN to prevent an output response greater than
14. This release time is the minimum time that /EN must be de-asserted prior to the next IN / /IN transition to affect the propagation delay of IN to Q
15. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles over a random sample of adjacent cycle pairs.
16. Total jitter definition: With an ideal clock input, no more than one output edge in 10
17. Random jitter definition: Jitter that is characterized by a Gaussian distribution, unbounded and is quantified by its standard deviation and mean.
February 2009
data. See timing diagram "Setup and Hold Time: SCLK and SLOAD.”
+75mv to the IN transition. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
less than 1ps. See timing diagram “Setup, Hold, and Release Time: IN and /EN.”
T
peak jitter value.
Random jitter is measured with a K28.7 comma defect pattern, measured at 1.5Gbps.
jitter_cc
= T
n
– T
n
+1, where T is the time between rising edges of the output signal.
8
12
output edges will deviate by more than the specified peak-to-
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