MC14536BDWR2G ON Semiconductor, MC14536BDWR2G Datasheet - Page 10

• Manufacturer Part Number: MC14536BDWR2G
• Description: IC TIMER PROG 24ST RIPPLE 16SOIC
• Manufacturer: ON Semiconductor
• Type: Programmable Timerr

Specifications of MC14536BDWR2G

• Frequency: 2MHz
• Voltage - Supply: 3 V ~ 18 V
• Current - Supply: 15µA
• Operating Temperature: -55°C ~ 125°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Number Of Internal Timers: 1
• Supply Voltage (max): 3 V to 18 V
• Supply Voltage (min): 3 V
• Maximum Power Dissipation: 500 mW
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Propagation Delay (max): 3600 ns @ 5 V or 1300 ns @ 10 V or 1000 ns @ 15 V
• # Internal Timers: 1
• Quiescent Current: 20uA
• Power Dissipation: 500mW
• Propagation Delay Time: 3600ns
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5/9/12/15V
• Operating Supply Voltage (max): 18V
• Package Type: SOIC W
• High Level Output Current: -4.2mA
• Low Level Output Current: 4.2mA
• Pin Count: 16
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: MC14536BDWR2GOS; MC14536BDWR2GOS; MC14536BDWR2GOSTR

NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET
DECODE OUT
input low enables the chip’s internal counters. After RESET goes low, the 2
DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2
intervals where n = the number of stages selected from the truth table.
RESET
CLOCK
PULSE
GEN.
IN
POWERUP
1
Figure 12. Time Interval Configuration Using an External Clock, Reset, and
*t
C
R
w
X
X
Output Monostable to Achieve a Pulse Output
(Divide−by−4 Configured)
10
12
15
14
11
6
9
2
1
7
3
http://onsemi.com
8−BYPASS
A
B
C
D
RESET
SET
CLOCK INH
MONO−IN
OSC INH
IN
1
MC14536B
10
V
V
+V
DD
SS
16
8
DECODE OUT
OUT 1
OUT 2
n
/2 negative transition of the clock input causes
13
4
5
*t
t
R
C
w
w
X
X
in msec
≈ .00247 • R
in kW
in pF
n
x (the clock period)
X
• C
X
0.85