CY2XF33FLXCT Cypress Semiconductor Corp, CY2XF33FLXCT Datasheet - Page 3

IC XTAL OSC CMOS 6CLCC

CY2XF33FLXCT

Manufacturer Part Number
CY2XF33FLXCT
Description
IC XTAL OSC CMOS 6CLCC
Manufacturer
Cypress Semiconductor Corp
Datasheets

Specifications of CY2XF33FLXCT

Pll
Yes
Input
Crystal
Output
LVDS
Number Of Circuits
1
Ratio - Input:output
1:1
Differential - Input:output
No/Yes
Frequency - Max
690MHz
Divider/multiplier
Yes/No
Voltage - Supply
*
Operating Temperature
*
Mounting Type
Surface Mount
Package / Case
6-CLCC
Frequency
*
Count
*
Operating Supply Voltage (typ)
2.5/3.3
Output Level
LVDS
Symmetry Max
60%
Operating Temp Range
0C to 70C
Screening Level
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Absolute Maximum Conditions
Operating Conditions
DC Electrical Characteristics
Document Number: 001-53148 Rev. *C
V
V
T
T
ESD
V
T
T
I
V
V
V
V
V
V
I
I
I
I
C
C
Parameter
Parameter
Parameter
Notes
DD
IH0
IH1
IL0
IL1
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers
3. I
4. Not 100% tested, guaranteed by design and characterization.
A
DD
IN
S
J
DD
PU
OD
OS
IH
IL
JA
IN0
IN1
OD
OS
[1]
[3]
[2]
are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
[4]
[4]
DD
HBM
includes ~4 mA of current that is dissipated externally in the output termination resistors.
3.3V Supply Voltage Range
2.5V Supply Voltage Range
Power Up Time for V
is Monotonic)
Ambient Temperature (Commercial)
Ambient Temperature (Industrial)
Operating Supply Current
LVDS Differential Output Voltage
Change in V
mentary Output States
LVDS Offset Output Voltage
Change in V
mentary Output States
Input High Voltage
Input Low Voltage
Input High Current, FS0 pin
Input High Current, FS1 pin
Input Low Current, FS0 pin
Input Low Current, FS1 pin
Input Capacitance, FS0 pin
Input Capacitance, FS1 pin
Supply Voltage
Input Voltage, DC
Temperature, Storage
Temperature, Junction
ESD Protection (Human Body Model)
Thermal Resistance, Junction to Ambient
Description
OD
OS
Description
between Comple-
between Comple-
DD
to Reach Minimum Specified Voltage (Power Ramp
Description
PRELIMINARY
V
terminated
V
terminated
V
as terminated in
V
as terminated in
V
as terminated in
V
between CLK and CLK#
Input = V
Input = V
Input = V
Input = V
DD
DD
DD
DD
DD
DD
= 3.3V or 2.5V, defined in
= 3.3V or 2.5V, defined in
= 3.3V or 2.5V, defined in
= 3.465V, CLK = 150 MHz, output
= 2.625V, CLK = 150 MHz, output
= 3.3V or 2.5V, R
Relative to V
Non operating
JEDEC STD 22-A114-B
0 m/s airflow
DD
DD
SS
SS
Condition
Figure 2
Figure 2
Figure 2
Condition
SS
TERM
= 100
Figure 3
Figure 3
Figure 4
0.7*V
3.135
2.375
1.125
0.05
Min
Min
247
–50
–20
–40
2000
–0.5
–0.5
Min
–55
–40
0
DD
Typ
64
Typ
3.3
2.5
15
4
V
DD
Max
135
135
4.4
0.3*V
+0.5
3.465
2.625
1.375
Max
500
Max
120
454
115
115
70
85
50
50
10
CY2XF33
DD
Page 3 of 7
C/W
Unit
Unit
Unit
C
C
ms
C
C
mA
mA
mV
mV
mV
V
V
V
V
V
A
A
A
A
pF
pF
V
V
V
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