DS4M133D+33 Maxim Integrated Products, DS4M133D+33 Datasheet - Page 6

• Manufacturer Part Number: DS4M133D+33
• Description: IC OSC CLOCK 133.33MHZ 10-LCCC
• Manufacturer: Maxim Integrated Products
• Type: Clock Oscillatorr

Specifications of DS4M133D+33

• Frequency: 133.33MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Current - Supply: 74mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 10-LCCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Count: -

3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
The DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
Figure 1. Functional Diagram
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
and Disabled
6
MS
_______________________________________________________________________________________
OUTN
OUTP
OE
0.7 x V
X1
X2
GND
CC
DS4M125/
DS4M133/
DS4M200
t
DECODER
P1A
THREE-
LEVEL
Detailed Description
THREE-
PHASE
STATE
DET
t
FILTER
PA1
0.3 x V
CC
DIVFB
LC-VCO
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100kΩ
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of V
outputs are a logical one. The OE pin has an internal
100kΩ pullup resistor. When the pin is left floating, the
device output is active.
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
and Disabled
DIVP
OUTN
OUTP
FREQUENCY SELECTION
OE
0.7 x V
PECL_BIAS
PECL_BIAS
CC
DIVOUT
t
PZA
OUTSELN
CC
- 2.0V, while the LVDS
OUTDRV
VCC
0.3 x V
t
PAZ
PECL_BIAS
PECL_BIAS
CC
OE
OUTP
OUTN