DS1073Z-270 Maxim Integrated Products, DS1073Z-270 Datasheet - Page 4

• Manufacturer Part Number: DS1073Z-270
• Description: ECONOSCILLATOR/DIV 270MHZ 8-SOIC
• Manufacturer: Maxim Integrated Products
• Series: EconOscillator™r
• Type: Oscillator, Fixed Frequency, Dualr

Specifications of DS1073Z-270

• Frequency: 270MHz
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Count: -

PIN DESCRIPTIONS
Output Pin (OUT1 pin): This pin is the main oscillator output.
Output Enable Function (OE pin): The DS1073 Special features a “synchronous” output enable. When
OE is at a high logic level the oscillator free runs. When this pin is taken low OUT1 is held low,
immediately if OUT1 is already low, or at the next high-to-low transition if OUT1 is high. This prevents
any possible truncation of the output pulse width when the enable is used. While the output is disabled
the master oscillator continues to run (producing an output at OUT0, if the EN0 bit = 0) but the internal
counters (/N) are reset. This results in a constant phase relationship between OE’s return to a high level
and the resulting OUT1 signal. When the enable is released OUT1 will make its first transition within
one to two clock periods of the master clock.
Power-Down (
(active low) and go into a reduced power consumption state. Internal “Enabling Sequencer” circuitry
will first disable OUT in the same way as when OE is used. Next OUT0 will be disabled in a similar
fashion. Finally the oscillator circuitry will be disabled. In this mode both outputs will go into a high
impedance state.
because the internal oscillator is completely powered down.
considerably longer to recover (i.e., achieve stable oscillation) from a power-down condition than if the
OE is used.
Reference Output (OUT0 pin): A reference output, OUT0, is also available from the output of the
prescaler. OUT0 is unaffected by the OE pin, but is disabled in a glitchless fashion if the device is
powered down. If this output is not required it can be permanently disabled and there will be a
corresponding reduction in overall power consumption. The availability of this output and its frequency
are specified on the special order form.
DNC: Do not connect.
OPERATION OF OUTPUT ENABLE
Since the output enable and internal master oscillator are asynchronous there is the possibility of timing
difficulties in the application.
sequencer” to produce predictable results when the device is enabled and disabled. In particular the
output gating is configured so that truncated output pulses can never be produced.
ENABLE TIMING
The output enable function is produced by sampling the OE input with the output from the pre-scaler mux
(MCLK) and gating this with the output from the programmable divider. The exact behavior of the
device is therefore dependent on the setup time (t
of MCLK. If the actual setup time is less than T
required to complete the enable or disable operation (see diagrams). This is unlikely to be of any
consequence in most applications, and then only if the value for N is small. In general, the output will
make its first positive transition between approximately one and two clock periods of MCLK after the
rising edge of OE. (Figure 2)
PDN
The power consumption in the power-down state is much less than if OE is used
pin): A low logic level on this pin can be used to make the device stop oscillating
To minimize these difficulties the DS1073 features an “enabling
SU
4 of 12
SUEM
) from a transition on the OE input to the rising edge
then one more complete cycle of MCLK will be
Consequently the device will take