M41T65Q6F STMicroelectronics, M41T65Q6F Datasheet - Page 13
![IC RTC SERIAL W/ALARM 16QFN](/photos/6/58/65816/m41t65q6f_sml.jpg)
M41T65Q6F
Manufacturer Part Number
M41T65Q6F
Description
IC RTC SERIAL W/ALARM 16QFN
Manufacturer
STMicroelectronics
Type
Clock/Calendar/Alarmr
Specifications of M41T65Q6F
Memory Size
16B
Time Format
HH:MM:SS:hh (24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.3 V ~ 4.4 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-QFN
Function
Clock/Calendar/Alarm/Timer Interrupt
Rtc Memory Size
16 Byte
Supply Voltage (max)
4.4 V
Supply Voltage (min)
1.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Rtc Bus Interface
Serial (2-Wire, I2C)
Supply Current
50 uA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-3908-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M41T65Q6F
Manufacturer:
VK
Quantity:
3 200
Part Number:
M41T65Q6F
Manufacturer:
ST
Quantity:
20 000
M41T62/63/64/65
2.1.4
2.1.5
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level put on the bus by the receiver whereas the master generates an extra acknowledge
related clock pulse. A slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the high period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line high to enable the master to generate the
STOP condition.
Figure 14. Serial bus data transfer sequence
CLOCK
DATA
CONDITION
START
Doc ID 10397 Rev 15
DATA VALID
DATA LINE
STABLE
DATA ALLOWED
CHANGE OF
CONDITION
STOP
Operation
AI00587
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