M41ST87WMX6TR STMicroelectronics, M41ST87WMX6TR Datasheet - Page 17

• Manufacturer Part Number: M41ST87WMX6TR
• Description: IC SUPERVISOR RTC 160X8 28-SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Supervisorr

Specifications of M41ST87WMX6TR

• Memory Size: 160B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC, 28-SOH (8.48mm Width)
• Bus Type: Serial (2-Wire, I2C)
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 28
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-6457-2; M41ST87WMX6TR

M41ST87Y, M41ST87W
Note:
2.5
2.6
2.6.1
Note:
power input is switched from the V
SRAM are maintained from the attached battery supply.
All outputs become high impedance. The V
M41ST87W) or 150µA (for M41ST87Y) of current to the attached memory with less than 0.3
volts drop under this condition. On power up, when V
protection continues for t
this time (see
Most low power SRAMs on the market today can be used with the M41ST87Y/W RTC
SUPERVISOR. There are, however some criteria which should be used in making the final
choice of an SRAM to use. The SRAM must be designed in a way where the chip enable
input disables all other inputs to the SRAM. This allows inputs to the M41ST87Y/W and
SRAMs to be “Don’t Care” once V
guarantee data retention down to V
sufficient to meet the system needs with the chip enable output propagation delays
included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to
V
If data retention lifetime is a critical parameter for the system, it is important to review the
data retention current specifications for the particular SRAMs being evaluated. Most SRAMs
specify a data retention current at 3.0 volts. Manufacturers generally specify a typical
condition for room temperature along with a worst case condition (generally at elevated
temperatures). The system level requirements will determine the choice of which value to
use. The data retention current value of the SRAMs can then be added to the I
the M41ST87Y/W to determine the total current requirements for data retention. The
available battery capacity for the battery of your choice can then be divided by this current to
determine the amount of data retention available.
For a further more detailed review of lifetime calculations, please see Application Note
AN1012.
Tamper detection circuit
The M41ST87Y/W provides two independent input pins, the tamper pin 1 input (TP1
tamper pin 2 input (TP2
result in the associated setting of the tamper bits (TB1 and/or TB2, in flag register 0Fh) if the
tamper enable bits (TEB1 and/or TEB2) are enabled, for the respective tamper 1 or tamper
2. The TP1
1) closing a switch to ground or V
previously closed to ground or V
bits and the TPM
Tamper register bits (tamper 1 and tamper 2)
Tamper enable bits (TEB1 and TEB2)
When set to a logic '1,' this bit will enable the tamper detection circuit. This bit must be set to
'0' in order to clear the associated tamper bits (TB
TEB
OUT
X
.
should be reset whenever the tamper detect condition is modified.
IN
pin or TP2
Figure 27 on page
X
bits in the tamper register (14h and/or 15h).
IN
IN
rec
), which can be used to monitor two separate signals which can
pin may be set to indicate a tamper event has occurred by either
by inhibiting E
OUT
43).
OUT
CC
CC
CC
(normally closed), depending on the state of the TCM
falls below V
pin to the battery, and the clock registers and external
(normally open), or by 2) opening a switch that was
= 2.0 volts. The chip enable access time must be
CON
OUT
. The RST signal also remains active during
pin is capable of supplying 100µA (for
PFD
X
, in 0Fh).
CC
(min). The SRAM should also
returns to a nominal value, write
Operating modes
BAT
value of
IN
) and
17/48
X