DS1687-5+ Maxim Integrated Products, DS1687-5+ Datasheet - Page 22

• Manufacturer Part Number: DS1687-5+
• Description: IC RTC 5V 64-BIT Y2K 24-EDIP
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1687-5+

• Memory Size: 242B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 24-DIP (600 mil) Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Extended Control Register 4B
ABE – Auxiliary Battery Enable. This bit when written to a logic 1 enables the V
E32K – Enable 32.768kHz output. This bit when written to a logic 1 enables the 32.768kHz oscillator frequency to
be output on the SQW pin. This bit is set to a logic 1 when V
CS – Crystal Select Bit. When CS is set to a 0, the oscillator is configured for operation with a crystal that has a
6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is disabled in the
DS1687 EDIP and should be set to CS = 0.
RCE – RAM Clear-Enable bit. When set to a 1, this bit enables a low level on RCLR to clear all 242 bytes of user
RAM. When RCE = 0, RCLR and the RAM clear function are disabled.
PRS – PAB Reset-Select Bit. When set to a 0, the PWR pin is set high-Z when the DS1685 goes into power-fail.
When set to a 1, the PWR pin remains active upon entering power-fail.
RIE – Ram Clear-Interrupt Enable. When RIE is set to a 1, the IRQ pin is driven low when a RAM clear function is
completed.
WIE – Wake-Up Alarm-Interrupt Enable. When V
active-low when a wake-up condition occurs, causing the WF bit to be set to 1. When V
pin is also driven low. If WIE is set while system power is applied, both IRQ and PWR are driven low in response to
WF being set to 1. When WIE is cleared to a 0, the WF bit has no affect on the PWR or IRQ pins.
KSE – Kickstart Interrupt Enable. When V
low when a kickstart condition occurs (KS pulsed low), causing the KF bit to be set to 1. When V
the IRQ pin is also driven low. If KSE is set to 1 while system power is applied, both IRQ and PWR are driven low in
response to KF being set to 1. When KSE is cleared to a 0, the KF bit has no affect on the PWR or IRQ pins.
SYSTEM MAINTENANCE INTERRUPT (SMI) RECOVERY STACK
An SMI recovery register stack is located in the extended register bank, locations 4Eh and 4Fh. This register stack,
shown below, can be used by the BIOS to recover from an SMI occurring during an RTC read or write.
BIT 7
MSB
ABE
BIT 6
E32K
DV0
7
AD6
6
BIT 5
CS
AD5
4Eh
4Fh
CC
5
REGISTER BIT DEFINITION
voltage is absent and KSE is set to a 1, the PWR pin is driven active-
BIT 4
RCE
CC
SMI RECOVERY STACK
AD4
4
voltage is absent and WIE is set to a 1, the PWR pin is driven
RTC ADDRESS-1
RTC ADDRESS-2
RTC ADDRESS-3
22 of 34
RTC ADDRESS
AD3
3
CC
is applied.
BIT 3
PRS
AD2
2
DS1685/DS1687 3V/5V Real-Time Clocks
BAUX
BIT 2
AD1
RIE
1
pin for extended functions.
CC
AD0
0
is then applied, the IRQ
BIT 1
WIE
CC
is then applied,
BIT 0
KSE
LSB