DS1744WP-120+ Maxim Integrated Products, DS1744WP-120+ Datasheet - Page 6

• Manufacturer Part Number: DS1744WP-120+
• Description: IC RTC RAM Y2K 3.3V 120NS 34-PCM
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAM/Y2Kr

Specifications of DS1744WP-120+

• Memory Size: 256K (32K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 34-PowerCap™ Module
• Function: Clock/Calendar/NV Timekeeping RAM
• Rtc Memory Size: 32768 Byte
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.97 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Supply Current: 75 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note: All indicated “X” bits are not used but must be set to a “0” during write cycle to ensure proper
clock operation.
Table 2. Register Map
RETRIEVING DATA FROM RAM OR CLOCK
The DS1744 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and
locations in the NV SRAM. Valid data is available at the DQ pins within t
stable, providing that the CE and OE access times and states are satisfied. If CE or OE access times and
states are not met, valid data is available at the latter of chip-enable access (t
time (t
the data lines are driven to an intermediate state until t
until the next address access.
WRITING DATA TO RAM OR CLOCK
The DS1744 is in the write mode whenever WE and CE are in their active state. The start of a write is
referenced to the latter occurring transition of WE or CE . The addresses must be held valid throughout
the cycle. CE or WE must return inactive for a minimum of t
write cycle. Data in must be valid t
typical application, the OE signal is high during a write cycle. However, OE can be active provided that
care is taken with the data bus to avoid bus contention. If OE is low prior to WE transitioning low, the
data bus can become active with read data defined by the address inputs. A low transition on WE then
disables the output t
CE (chip enable) is low. The device architecture allows ripple-through access to any of the address
OE remain valid, output data remains valid for output-data hold time (t
ADDRESS
OSC = Stop Bit
W = Write Bit
7FFD
7FFC
7FFB
7FFA
7FFF
7FFE
7FF9
7FF8
OEA
). The state of the DQ pins is controlled by CE and OE . If the outputs are activated before t
OSC
BF
B7
W
X
X
X
X
WEZ
B6
FT
after WE goes active.
X
X
X
R
10 Year
R = Read Bit
X = See Note
10 Seconds
10 Minutes
B5
X
X
10 Century
10 Hour
10 Date
DS
prior to the end of write and remain valid for t
Month
B4
10
X
DATA
DS1744/DS1744P Y2K-Compliant, Nonvolatile Timekeeping RAMs
6 of 16
B3
X
AA
. If the address inputs are changed while CE and
B2
Minutes
Seconds
Century
Month
WR
Hour
Year
Date
FT = Frequency Test
BF = Battery Flag
prior to the initiation of another read or
Day
B1
OH
AA
) but then goes indeterminate
CEA
B0
after the last address input is
) or at output-enable access
FUNCTION
Seconds
Minutes
Century
Month
DH
Hour
Year
Date
Day
afterward. In a
RANGE
00-99
01-12
01-31
01-07
00-23
00-59
00-39
00-59
AA
,