M41T0M6E STMicroelectronics, M41T0M6E Datasheet - Page 10

• Manufacturer Part Number: M41T0M6E
• Description: IC RTC SERIAL 2V-5.5V 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T0M6E

• Memory Size: 8B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar
• Rtc Memory Size: 8 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (2-Wire, I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2812-5; M41T0M6

2.2
10/22
Table 2.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300 ns max.) of the falling
READ mode
In this mode, the master reads the M41T0 slave after setting the slave address (see
Figure
word address An is written to the on-chip address pointer. Next the START condition and
slave address are repeated, followed by the READ mode control bit (R/W = 1). At this point,
the master transmitter becomes the master receiver. The data byte which was addressed
will be transmitted and the master receiver will send an acknowledge bit to the slave
transmitter. The address pointer is only incremented on reception of an acknowledge bit.
The M41T0 slave transmitter will now place the data byte at address A
master receiver reads and acknowledges the new byte and the address pointer is
incremented to A
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T0
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer (see
t
Symbol
HD:DAT
t
t
t
t
SU:STO
HD:STA
SU:STA
SU:DAT
t
t
edge of SCL.
f
t
HIGH
LOW
BUF
SCL
t
t
R
F
7). Following the WRITE mode control bit (R/W = 0) and the acknowledge bit, the
(2)
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
START condition setup time
(only relevant for a repeated start condition)
Data setup time
Data hold time
STOP condition setup time
Time the bus must be free before a new transmission
can start
AC characteristics
n+2
.
Parameter
Figure 9 on page
A
= –40 to 85°C; V
(1)
12).
CC
= 2.0 to 5.5 V (except where noted).
Min
600
600
600
100
600
1.3
1.3
0
0
n+1
Typ
on the bus. The
Max
400
300
300
Unit
kHz
ns
µs
ns
ns
ns
ns
ns
ns
µs
µs