IDT1339C-31SOGI8 IDT, Integrated Device Technology Inc, IDT1339C-31SOGI8 Datasheet - Page 9

• Manufacturer Part Number: IDT1339C-31SOGI8
• Description: IC SERIAL RTC I2C LP 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Calendar/Alarmr

Specifications of IDT1339C-31SOGI8

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3.3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 1339C-31SOGI8

Table 5. SQW/INT Output
Status Register (0Fh)
IDT® REAL-TIME CLOCK WITH SERIAL I
INTCN
IDT1339
REAL-TIME CLOCK WITH SERIAL I
Bit 7
OSF
0
0
0
0
1
1
1
Bit 2: Interrupt Control (INTCN). This bit controls the relationship between the two alarms and the interrupt output
pins. When the INTCN bit is set to logic 1, a match between the timekeeping registers and the alarm 1 or alarm 2
registers activate the SQW/INT pin (provided that the alarm is enabled). When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin. This bit is set to logic 0 when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to a logic 1, this bit permits the Alarm 2 Flag (A2F) bit in the
status register to assert SQW/INT (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0,
the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the Alarm 1 Flag (A1F) bit in the status
register to assert SQW/INT (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F
bit does not initiate an interrupt signal. The A1IE bit is disabled (logic 0) when power is first applied.
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped
for some period of time and may be used to judge the validity of the clock and date data. This bit is edge triggered
and is set to logic 1 when the oscillator stops. The following are examples of conditions that can cause the OSF bit
to be set:
1) The first time power is applied.
2) The voltage on both
3) The EOSC bit is turned off.
4) External influences on the crystal (e.g., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to a logic 0.
Bit 1: Alarm 2 Flag (A2F). A logic 1 in the Alarm 2 Flag bit indicates that the time matched the alarm 2 registers. If
the A2IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A2F is cleared when
written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A logic 1 in the Alarm 1 Flag bit indicates that the time matched the alarm 1 registers. If
the A1IE bit is a logic 1 and the INTCN bit is set to a logic 1, the SQW/INT pin is also asserted. A1F is cleared when
written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged.
RS2
0
0
1
1
X
X
X
Bit 6
0
RS1
0
1
0
1
X
X
X
Bit 5
0
SQW/INT Output
V
CC
2
C INTERFACE
32.768 kHz
A2F + A1F
4.096 kHz
8.192 kHz
and V
2
C INTERFACE
Bit 4
1 Hz
A1F
A2F
0
BACKUP
Bit 3
are insufficient to support oscillation.
0
A2IE
X
X
X
X
0
1
1
Bit 2
0
9
A1IE
X
X
X
X
1
0
1
Bit 1
A2F
Bit 0
A1F
IDT1339
REV K 032910
RTC