IDT1339C-2SOGI IDT, Integrated Device Technology Inc, IDT1339C-2SOGI Datasheet - Page 4

• Manufacturer Part Number: IDT1339C-2SOGI
• Description: IC SERIAL RTC I2C LP 16-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock/Calendar/Alarmr

Specifications of IDT1339C-2SOGI

• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Other names: 1339C-2SOGI

ESR (Effective Series Resistance)
Choose the crystal with lower ESR. A low ESR helps the
crystal to start up and stabilize to the correct output
frequency faster compared to high ESR crystals.
Frequency Tolerance
The frequency tolerance for 32 KHz crystals should be
specified at nominal temperature (+25°C) on the crystal
manufacturer datasheet. The crystals used with IDT1338
typically have a frequency tolerance of ±20ppm at +25°C.
Specifications for a typical 32 kHz crystal used with our
device are shown in the table below.
PCB Design Consideration
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•
•
•
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IDT® REAL-TIME CLOCK WITH SERIAL I
Series Resistance
Load Capacitance
IDT1339
REAL-TIME CLOCK WITH SERIAL I
Signal traces between IDT device pins and the crystal
must be kept as short as possible. This minimizes
parasitic capacitance and sensitivity to crosstalk and
EMI. Note that the trace capacitances play a role in the
effective crystal load capacitance calculation.
Data lines and frequently switching signal lines should be
routed as far away from the crystal connections as
possible. Crosstalk from these signals may disturb the
oscillator signal.
Reduce the parasitic capacitance between X1 and X2
signals by routing them as far apart as possible.
The oscillation loop current flows between the crystal and
the load capacitors. This signal path (crystal to CL1 to
CL2 to crystal) should be kept as short as possible and
ideally be symmetric. The ground connections for both
capacitors should be as close together as possible.
Never route the ground connection between the
capacitors all around the crystal, because this long
ground trace is sensitive to crosstalk and EMI.
To reduce the radiation / coupling from oscillator circuit,
an isolated ground island on the GND layer could be
made. This ground island can be connected at one point
to the GND layer. This helps to keep noise generated by
the oscillator circuit locally on this separated island. The
ground connections for the load capacitors and the
oscillator should be connected to this island.
Nominal Freq.
Parameter
Symbol
ESR
C
f
O
L
Min
2
C INTERFACE
2
32.768
C INTERFACE
Typ
7
Max Units
50
kHz
k
pF
4
PCB Layout
PCB Assembly, Soldering and Cleaning
Board-assembly production process and assembly quality
can affect the performance of the 32 kHz oscillator.
Depending on the flux material used, the soldering process
can leave critical residues on the PCB surface. High
humidity and fast temperature cycles that cause humidity
condensation on the printed circuit board can create
process residuals. These process residuals cause the
insulation of the sensitive oscillator signal lines towards
each other and neighboring signals on the PCB to decrease.
High humidity can lead to moisture condensation on the
surface of the PCB and, together with process residuals,
reduce the surface resistivity of the board. Flux residuals on
the board can cause leakage current paths, especially in
humid environments. Thorough PCB cleaning is therefore
highly recommended in order to achieve maximum
performance by removing flux residuals from the board after
assembly. In general, reduction of losses in the oscillator
circuit leads to better safety margin and reliability.
Power Control
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the
fully accessible and data can be written and read when
is greater than V
internal clock registers are blocked from any access. If V
is less than V
to V
V
when
maintained from the V
nominal levels (Table 1). After
and write access is allowed after t
“Power-Up/Down Timing” diagram).
BACKUP
BACKUP
V
CC
, the device power is switched from
drops below V
when
BACKUP
PF
V
. However, when
CC
, the device power is switched from
drops below V
BACKUP
BACKUP
source until
V
CC
. The registers are
REC
returns above V
IDT1339
V
V
PF
CC
CC
. If V
(see the
falls below V
level. The device is
1339
V
PF
CC
V
is greater than
CC
is returned to
REV K 032910
to V
PF
BACKUP
PF
, read
RTC
, the
V
V
CC
PF
CC