M48T18-100PC1 STMicroelectronics, M48T18-100PC1 Datasheet - Page 8

• Manufacturer Part Number: M48T18-100PC1
• Description: IC TIMEKPR NVRAM 64KBIT 5V 28-DI
• Manufacturer: STMicroelectronics
• Series: Timekeeper®r
• Type: Clock/Calendar/NVSRAMr

Specifications of M48T18-100PC1

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 28-DIP Module (600 mil), 28-EDIP
• Function: Clock/Calendar/NV Timekeeping RAM/Battery Backup
• Rtc Memory Size: 8192 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Rtc Bus Interface: Parallel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2837-5

Operation modes
2
Note:
8/31
Operation modes
As
oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible
BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24-hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 1FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y
includes a clock control circuit which updates the clock bytes with current information once
per second. The information can be accessed by the user in the same manner as any other
location in the static memory array.
The M48T08/18/08Y also has its own power-fail detect circuit. The control circuitry
constantly monitors the single 5 V supply for an out-of-tolerance condition. When V
of tolerance, the circuit write protects the SRAM, providing a high degree of data security in
the midst of unpredictable system operation brought on by low V
battery backup switchover voltage (V
maintains data and clock operation until valid power returns.
Table 2.
1. See
X = V
Deselect
Deselect
WRITE
READ
READ
Deselect
Deselect
Mode
Figure 4 on page 7
IH
Table 11 on page 22
or V
4.75 to 5.5 V
V
4.5 to 5.5 V
IL
Operating modes
PFD
; V
V
V
V
SO
(min)
or
SO
CC
SO
to
(1)
= Battery backup switchover voltage.
(1)
shows, the static memory array and the quartz-controlled clock
for details.
V
E1
V
V
V
X
X
X
IH
IL
IL
IL
Doc ID 2411 Rev 10
V
V
V
V
E2
X
X
X
SO
IH
IH
IH
IL
), the control circuitry connects the battery which
V
V
G
X
X
X
X
X
IH
IL
V
V
V
W
X
X
X
X
IH
IH
IL
DQ0-DQ7
High Z
High Z
High Z
High Z
High Z
D
D
M48T08, M48T08Y, M48T18
OUT
IN
CC
. As V
Battery backup mode
CC
CMOS standby
falls below the
Standby
Standby
Power
Active
Active
Active
CC
is out