DS3232S#T&R Maxim Integrated Products, DS3232S#T&R Datasheet - Page 15

• Manufacturer Part Number: DS3232S#T&R
• Description: IC RTC W/TCXO 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/TCXO/Crystalr

Specifications of DS3232S#T&R

• Memory Size: 236B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The aging offset register takes a user-provided value to
add to or subtract from the oscillator capacitor array.
The data is encoded in two’s complement, with bit 7
representing the sign bit. One LSB represents the
smallest capacitor to be switched in or out of the
capacitance array at the crystal pins. The aging offset
register capacitance value is added or subtracted from
the capacitance value that the device calculates for
each temperature compensation. The offset register is
added to the capacitance array during a normal tem-
perature conversion, if the temperature changes from
the previous conversion, or during a manual user con-
version (setting the CONV bit). To see the effects of the
aging register on the 32kHz output frequency immedi-
ately, a manual conversion should be started after each
aging offset register change.
Positive aging values add capacitance to the array,
slowing the oscillator frequency. Negative values
remove capacitance from the array, increasing the
oscillator frequency.
The change in ppm per LSB is different at different
temperatures. The frequency vs. temperature curve is
shifted by the values used in this register. At +25°C,
* POR is defined as the first application of power to the device, either V
NAME:
NAME:
NAME:
NAME:
POR*:
POR*:
POR*:
POR*:
BIT 7
SIGN
DATA
BIT 7
BIT 7
SIGN
BIT 7
D7
0
X
0
0
Aging Offset Register
DATA
BIT 6
DATA
DATA
BIT 6
BIT 6
BIT 6
D6
0
X
0
0
Extremely Accurate I
____________________________________________________________________
DATA
BIT 5
DATA
BIT 5
BIT 5
BIT 5
D5
0
X
0
0
0
Integrated Crystal and SRAM
Temperature Register (Lower Byte) (12h)
Temperature Register (Upper Byte) (11h)
DATA
BIT 4
DATA
BIT 4
BIT 4
BIT 4
D4
0
X
0
0
0
one LSB typically provides about 0.1ppm change in
frequency.
Use of the aging register is not needed to achieve the
accuracy as defined in the EC tables, but could be
used to help compensate for aging at a given tempera-
ture. See the Typical Operating Characteristics section
for a graph showing the effect of the register on accu-
racy over temperature.
Temperature is represented as a 10-bit code with a res-
olution of 0.25°C and is accessible at location 11h and
12h. The temperature is encoded in two’s complement
format, with bit 7 in the MSB representing the sign bit.
The upper 8 bits, the integer portion, are at location 11h
and the lower 2 bits, the fractional portion, are in the
upper nibble at location 12h. For example,
00011001 01b = +25.25°C. Upon power reset, the reg-
isters are set to a default temperature of 0°C and the
controller starts a temperature conversion.
The temperature is read on initial application of V
I
wards. The temperature registers are updated after
each user-initiated conversion and on every 64-second
conversion. The temperature registers are read-only.
2
BAT
C access on V
Temperature Registers (11h–12h)
or V
DATA
BIT 3
DATA
BIT 3
BIT 3
BIT 3
D3
0
X
0
0
0
CC
.
BAT
DATA
BIT 2
DATA
BIT 2
BIT 2
BIT 2
D2
0
X
0
0
0
and once every 64 seconds after-
2
Aging Offset (10h)
C RTC with
SRAM (14h–FFh)
DATA
BIT 1
DATA
BIT 1
BIT 1
BIT 1
D1
0
0
0
X
0
DATA
BIT 0
DATA
BIT 0
BIT 0
BIT 0
D0
0
0
0
X
0
CC
15
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