DS32C35-33IND# Maxim Integrated Products, DS32C35-33IND# Datasheet - Page 17

• Manufacturer Part Number: DS32C35-33IND#
• Description: IC RTC W/TCXO 20-SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/TCXO/Crystal/FRAMr

Specifications of DS32C35-33IND#

• Memory Size: 64K (8K x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Function: Clock/Calendar
• Rtc Memory Size: 8192 B
• Supply Voltage (max): 3.63 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 260 uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The DS32B35/DS32C35 support a bidirectional I
and data transmission protocol (Figure 1). A device that
sends data onto the bus is defined as a transmitter, and
a device receiving data is defined as a receiver. The
device that controls the message is called a master. The
devices that are controlled by the master are slaves.
The bus must be controlled by a master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions. The device operates as a slave on the I
Connections to the bus are made through the SCL input
Figure 1. Data Transfer on I
Figure 2. I
SDA
SCL
SDA
SCL
CONDITION
START
STOP
2
C Data Transfer Overview
t
BUF
START
MSB
1
2
I
C Serial Bus
t
2
HD:STA
2
t
LOW
SLAVE ADDRESS
C Serial Data Bus
Accurate I
t
R
6
____________________________________________________________________
t
HD:DAT
7
t
F
DIRECTION
t
HIGH
2
2
R/W
C bus.
BIT
C bus
8
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
t
SU:DAT
ACK
9
2
and open-drain SDA I/O lines. Within the bus specifica-
tions, a standard mode (100kHz maximum clock rate)
and a fast mode (400kHz maximum clock rate) are
defined. The DS32B35/DS32C35 work in both modes.
The following bus protocol has been defined (Figure 2):
• Data transfer can be initiated only when the bus is
• During data transfer, the data line must remain stable
C RTC with Integrated
not busy.
whenever the clock line is high. Changes in the data
line while the clock line is high are interpreted as
control signals.
REPEATED
START
TCXO/Crystal/FRAM
1
t
SU:STA
t
HD:STA
2
REPEATED IF MORE BYTES
ARE TRANSFERED
3–7
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
8
ACK
9
t
SP
t
SU:STO
OR REPEATED
CONDITION
CONDITION
START
STOP
17