M48T35Y-70MH6F STMicroelectronics, M48T35Y-70MH6F Datasheet - Page 10
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M48T35Y-70MH6F
Manufacturer Part Number
M48T35Y-70MH6F
Description
IC TIMEKPR NVRAM 256KB 5V 28SOIC
Manufacturer
STMicroelectronics
Series
Timekeeper®r
Type
Clock/Calendar/NVSRAMr
Datasheet
1.M48T35Y-70MH1E.pdf
(28 pages)
Specifications of M48T35Y-70MH6F
Memory Size
256K (32K x 8)
Time Format
HH:MM:SS (24 hr)
Date Format
YY-MM-DD-dd
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC, 28-SOH (8.48mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-4717-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Operation modes
2.2
Figure 6.
Figure 7.
10/28
A0-A14
E
W
DQ0-DQ7
A0-A14
E
W
DQ0-DQ7
WRITE mode
The M48T35/Y is in the WRITE mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
to the initiation of another READ or WRITE cycle. Data-in must be valid t
end of WRITE and remain valid for t
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
WRITE enable controlled, WRITE AC waveform
Chip enable controlled, WRITE AC waveforms
tAVEL
tAVEL
tAVWL
tAVWL
tWLQZ
Doc ID 2611 Rev 9
tAVWH
tAVEH
EHAX
tWLWH
VALID
tAVAV
VALID
tAVAV
WHDX
tELEH
from chip enable or t
afterward. G should be kept high during WRITE
WLQZ
tDVEH
tDVWH
DATA INPUT
after W falls.
DATA INPUT
tWHDX
WHAX
tEHDX
tWHQX
tEHAX
from WRITE enable prior
tWHAX
M48T35, M48T35Y
DVWH
prior to the
AI00926
AI00927