MAXQ3183-RAN+ Maxim Integrated Products, MAXQ3183-RAN+ Datasheet - Page 24

• Manufacturer Part Number: MAXQ3183-RAN+
• Description: IC AFE POLYPHASE MULTI 28TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAXQ3183-RAN+

• Number Of Channels: 8
• Power (watts): 140mW
• Voltage - Supply, Analog: 3.6V
• Voltage - Supply, Digital: 3.6V
• Package / Case: 28-TSSOP
• For Use With: MAXQ3183-KIT - KIT EV REFRNC DSIGN FOR MAXQ3183
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Bits: -
• Other names: 90-M3183+RAN

Low-Power, Multifunction, Polyphase AFE
with Harmonics and Tamper Detect
Figures 5 and 6 show typical 2-byte reading and writing
transfers (without CRC byte).
Individual message bytes sent through the SPI are
processed in a software routine contained in the ROM
firmware. For this reason, it is necessary to provide a
delay between successive bytes. This byte spacing
must be no less than 400 system clocks to ensure that
the MAXQ3183 has a chance to read and process the
byte before the arrival of the next one. It is strongly rec-
ommended that CRC be enabled for both read and
write to achieve reliable operations.
Data and device command and control information are
located in internal registers. Registers range from 8 to 64
bits in length and are divided into RAM-based registers
Figure 5. Read SPI Transfer
Figure 6. Write SPI Transfer
24
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SCLK
MOSI
MISO
SCLK
MOSI
MISO
SSEL
SSEL
00 01
10 01
0xC1
0xC1
Host Software Design
ADDRESS
ADDRESS
Register Set
0xC2
0xC2
WRITING DATA TO MAXQ3183 THROUGH SPI INTERFACE
READING DATA FROM MAXQ3183 THROUGH SPI INTERFACE
NACK (0x4E)
ACK (0x41)
DATA LSB
DUMMY
and virtual registers. The RAM-based registers contain
both operating parameters and measurement results.
To read any virtual power registers, the host must first
confirm that the DSPRDY bit of the IRQ_FLAG register
is set, which indicates the last DSP cycle has complet-
ed, then proceed to reading all the desired virtual
power registers. For best communication efficiency, it is
recommended to complete reading the virtual power
registers before reading other registers. Virtual power
register reads must be completed within 50% of DSP
cycle time, from the moment DSPRDY bit is set. Do not
forget to clear the DSPRDY bit, otherwise, host software
is not able to detect the completion of the new DSP
cycle. The MAXQ3183 does not clear the bit; it only
sets the bit whenever a DSP cycle processing is com-
pleted. Users can clear the bit directly after the confir-
mation that the bit is set. Clearing the DSPRDY bit does
not affect the DSP processing.
ACK (0x41)
DATA MSB
ACK (0x41)
DUMMY
NACK (0x4E)
DATA LSB
DUMMY
DUMMY
ACK (0x41)
DATA MSB
DUMMY
DUMMY