MAX19710ETN+T Maxim Integrated Products, MAX19710ETN+T Datasheet - Page 18

• Manufacturer Part Number: MAX19710ETN+T
• Description: IC ANLG FRNT END 56-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX19710ETN+T

• Number Of Bits: 10
• Number Of Channels: 2
• Power (watts): 30mW
• Voltage - Supply, Analog: 3V
• Voltage - Supply, Digital: 3V
• Package / Case: 56-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Tx DAC outputs (IDN, IDP, QDN, QDP) are biased at
an adjustable common-mode DC level and designed to
drive a differential input stage with ≥ 70kΩ input imped-
ance. This simplifies the analog interface between RF
quadrature upconverters and the MAX19710. Many RF
upconverters require a 0.89V to 1.36V common-mode
bias. The MAX19710 common-mode DC bias eliminates
discrete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC. The Tx DAC differential analog outputs can-
not be used in single-ended mode because of the
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
18
18
Figure 3. Rx ADC System Timing Diagram
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode V
Full Scale)
DIFFERENTIAL OUTPUT VOLTAGE (V)
______________________________________________________________________________________
______________________________________________________________________________________
D0–D9
QA
CLK
t
DOQ
IA
(
(
(
(
(
(
(
V
V
V
V
V
V
V
FS
FS
FS
FS
FS
FS
FS
)
)
)
)
)
)
)
V
V
V
V
V
V
V
t
CL
REFDAC
REFDAC
REFDAC
REFDAC
REFDAC
REFDAC
REFDAC
D0Q
1024
1024
1024
1024
1024
1024
1024
t
CLK
t
CH
D1I
×
×
×
×
×
×
×
1023
1023
1023
1023
1023
1023
1023
1023
1023
1023
1023
1023
1023
1023
REFDAC
t
DOI
D1Q
= 1.024V, External Reference Mode V
D2I
D2Q
OFFSET BINARY (DA0–DA9)
5.5 CLOCK-CYCLE LATENCY (QA)
5 CLOCK-CYCLE LATENCY (IA)
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
D3I
D3Q
internally generated common-mode DC level. Table 2
shows the Tx DAC output voltage vs. input codes. Table
10 shows the selection of DC common-mode levels.
See Figure 4 for an illustration of the Tx DAC analog
output levels.
The Tx DAC also features independent DC offset trim on
each ID–QD channel. This feature is configured through
the SPI interface. The DC offset correction is used to opti-
mize sideband and carrier suppression in the Tx signal
path (see Table 9).
D4I
REFDAC
D4Q
D5I
= V
REFIN
INPUT DECIMAL CODE
D5Q
, V
FS
1023
1022
513
512
511
D6I
1
0
= 400 for 800mV
D6Q
P-P