AD9879BS Analog Devices Inc, AD9879BS Datasheet - Page 2

• Manufacturer Part Number: AD9879BS
• Description: IC FRONT-END MIXED-SGNL 100-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9879BS

• Rohs Status: RoHS non-compliant
• Number Of Bits: 12
• Number Of Channels: 5
• Power (watts): 587mW
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Package / Case: 100-MQFP, 100-PQFP

AD9879
TABLE OF CONTENTS
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 7
Pin Configuration and Function Descriptions............................. 8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Register Map and Bit Definitions ................................................. 16
Explanation of Test Levels ........................................................... 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Transmit Path.............................................................................. 11
Data Assembler........................................................................... 11
Interpolation Filter ..................................................................... 12
Digital Upconverter.................................................................... 12
DPLL-A Clock Distribution...................................................... 12
Clock and Oscillator Circuitry ................................................. 12
Programmable Clock Output REFCLK................................... 13
Reset and Transmit Power-Down ............................................ 14
Σ-Δ Outputs ................................................................................ 15
Register 0x00—Initialization .................................................... 17
Register 0x01—Clock Configuration....................................... 17
Register 0x02—Power-Down.................................................... 17
Registers 0x03–0x04—Σ-Δ and Flag Control......................... 17
Register 0x07—Video Input Configuration............................ 17
Register 0x08—ADC Clock Configuration ............................ 18
Register 0x0C—Die Revision.................................................... 18
Register 0x0D—Tx Frequency Tuning Words LSBs.............. 18
Register 0x0E—DAC Gain Control ......................................... 18
Register 0x0F—Tx Path Configuration ................................... 18
Registers 0x10–0x17—Carrier Frequency Tuning................. 19
Rev. A | Page 2 of 32
Serial Interface for Register Control ............................................ 20
Transmit Path (Tx) ......................................................................... 22
Programming the AD8321/AD8323 or AD8322/AD8327 Cable
Driver Amplifier Gain Control..................................................... 26
Receive Path (Rx) ........................................................................... 27
PCB Design Considerations.......................................................... 28
Outline Dimensions ....................................................................... 30
General Operation of the Serial Interface............................... 20
Instruction Byte .......................................................................... 20
Serial Interface Port Pin Description....................................... 20
MSB/LSB Transfers .................................................................... 20
Notes on Serial Port Operation ................................................ 21
Transmit Timing......................................................................... 22
Data Assembler........................................................................... 22
Half-Band Filters (HBFs) .......................................................... 22
Cascaded Integrator-Comb (CIC) Filter................................. 22
Combined Filter Response........................................................ 22
Tx Signal Level Considerations ................................................ 24
Tx Throughput and Latency ..................................................... 24
Digital-to-Analog Converter .................................................... 25
IF10 and IF12 ADC Operation ................................................ 27
Input Signal Range and Digital Output Codes....................... 27
Driving the Inputs ...................................................................... 27
Component Placement .............................................................. 28
Power Planes and Decoupling .................................................. 28
Ground Planes ............................................................................ 29
Signal Routing............................................................................. 29
Ordering Guide .......................................................................... 30