AD73311LARS Analog Devices Inc, AD73311LARS Datasheet - Page 14

IC ANALOG FRONT END 20-SSOP

AD73311LARS

Manufacturer Part Number
AD73311LARS
Description
IC ANALOG FRONT END 20-SSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD73311LARS

Rohs Status
RoHS non-compliant
Number Of Bits
16
Number Of Channels
2
Power (watts)
50mW
Voltage - Supply, Analog
3V
Voltage - Supply, Digital
3V
Package / Case
20-SSOP

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AD73311L
CONTROL REGISTER A
CONTROL REGISTER B
CONTROL REGISTER C
RESET
CEE
7
7
7
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
Bit
0
1
2
3
4
5
6
7
MCD2
DC2
Name
DATA/PGM
MM
DLB
SLB
DC0
DC1
DC2
RESET
Name
DIR0
DIR1
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Name
PU
Reserved
Reserved
PUADC
PUDAC
PUREF
RU
Reserved
RU
6
6
6
Table XIII. Control Register C Description
Table XII. Control Register B Description
Table XI. Control Register A Description
PUREF
MCD1
DC1
5
5
5
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Description
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = Off; 1 = Enabled)
Digital Loop-Back Mode (0 = Off; 1 = Enabled)
SPORT Loop-Back Mode (0 = Off; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = Off; 1 = Initiates Reset)
Description
Decimation/Interpolation Rate (Bit 0)
Decimation/Interpolation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
Control Echo Enable (0 = Off; 1 = Enabled)
Description
Power-Up Device (0 = Power Down; 1 = Power On)
ADC Power (0 = Power Down; 1 = Power On)
DAC Power (0 = Power Down; 1 = Power On)
REF Power (0 = Power Down; 1 = Power On)
REFOUT Use (0 = Disable REFOUT; 1 = Enable
REFOUT)
MCD0
PUDAC
DC0
4
4
4
SCD1
PUADC
SLB
3
3
3
SCD0
DLB
2
2
2
DIR1
MM
1
1
1
DATA/PGM
DIR0
PU
0
0
0

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