AD73322LARU Analog Devices Inc, AD73322LARU Datasheet - Page 28

• Manufacturer Part Number: AD73322LARU
• Description: IC ANALOG FRONT END DUAL 28TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD73322LARU

• Rohs Status: RoHS non-compliant
• Number Of Bits: 16
• Number Of Channels: 4
• Power (watts): 73mW
• Voltage - Supply, Analog: 2.7 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP

AD73322L
Each bit will take 1/SCLK and, allowing for any latency between
the receipt of the Rx interrupt and the transmission of the Tx
data, the relationship for successful operation is given by
The interrupt latency will include the time between the ADC
sampling event and the Rx interrupt being generated in the
DSP—this should be 16 SCLK cycles.
Because the AD73322L is configured in cascade mode, each
device must know the number of devices in the cascade because
the data and mixed modes use a method of counting input
frame sync pulses to decide when they should update the DAC
register from the serial input register. Control Register A
contains a 3-bit field (DC0-2) that is programmed by the DSP
during the programming phase. The default condition is that
the field contains 000b, which is equivalent to a single device in
the cascade (see Table 26). However, for cascade operation this
field must contain a binary value that is one less than the
number of devices in the cascade, which is 001b for a single
AD73322L device configuration.
M/DMCLK > ((N × 16/SCLK) + T
INTERRUPT LATENCY
)
Rev. A | Page 28 of 48
Table 26. Device Count Settings
DC2
0
0
0
0
1
1
1
1
DC1
0
0
1
0
0
1
1
DC0
0
1
0
1
0
1
0
1
Cascade Length
1
2
3
4
5
6
7
8