AD7921ARM-REEL7 Analog Devices Inc, AD7921ARM-REEL7 Datasheet - Page 7

• Manufacturer Part Number: AD7921ARM-REEL7
• Description: IC ADC 12BIT DUAL LP 8-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7921ARM-REEL7

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 20mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: AD7921ARM-REEL7TR

TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
V
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
TIMING DIAGRAMS
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Mark/space ratio for SCLK input is 40/60 to 60/40.
Minimum f
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross V
Measured with a 50 pF load capacitor.
T
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of the bus loading.
See the Power-Up Time section.
3
3
4
DD
10
5
DOUT
SCLK
1
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
= 2.35 V to 5.25 V; T
Figure 2. Load Circuit for Digital Output Timing Specifications
6
SCLK
at which specifications are guaranteed.
Figure 3. Access Time after SCLK Falling Edge
TO OUTPUT
Limit at T
10
5
16 × t
14 × t
30
15
10
30
45
0.4 t
0.4 t
10
5
6
30
10
1
PIN
SCLK
SCLK
50pF
SCLK
SCLK
t
A
4
C
= T
L
MIN
200µA
200µA
MIN
, T
to T
MAX
MAX
I
I
OL
OH
, unless otherwise noted.
Unit
kHz min
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
µs max
1.6V
2
V
V
Description
AD7921
AD7911
Minimum quiet time required between bus relinquish and start of next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until DOUT three-state is disabled
DOUT access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to DOUT valid hold time
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
SCLK falling edge to DOUT three-state
SCLK falling edge to DOUT three-state
Power-up time from full power-down
IH
IL
Rev. 0 | Page 7 of 28
DD
) and timed from a voltage level of 1.6 V.
DOUT
DOUT
SCLK
SCLK
V
V
IH
IH
IL
10
or V
, quoted in the timing characteristics is the true bus relinquish
Figure 5. SCLK Falling Edge to DOUT Three-State
IL
Figure 4. Hold Time after SCLK Falling Edge
voltage.
t
7
t
10
AD7911/AD7921
1.6V