AD7904BRUZ Analog Devices Inc, AD7904BRUZ Datasheet - Page 21

• Manufacturer Part Number: AD7904BRUZ
• Description: IC ADC 8BIT 4CH 1MSPS 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7904BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Number Of Converters: 1
• Power Dissipation (max): 13.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 8bit
• Sampling Rate: 1MSPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Current: 2.7mA
• Digital Ic Case Style: TSSOP
• Package: 16TSSOP
• Resolution: 8 Bit
• Architecture: SAR
• Number Of Adcs: 1
• Number Of Analog Inputs: 4
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Signal To Noise Ratio: 49(Min) dB
• Polarity Of Input Voltage: Unipolar
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD79X4CBZ - BOARD EVALUATION FOR AD79X4CBZ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Figure 15 shows the maximum power versus throughput rate
when using the Auto Shutdown mode with 5 V and 3 V supplies.
REV. 0
Figure 15. AD7924 Power vs. Throughput Rate
0.01
0.1
10
DOUT
DOUT
DOUT
1
SCLK
SCLK
SCLK
0
DIN
DIN
DIN
CS
CS
CS
THREE-
STATE
THREE-
STATE
THREE-
STATE
V
t
t
t
t
t
t
DD
2
3
2
3
2
3
50
= 5V
ZERO
ZERO
ZERO
WRITE
WRITE
WRITE
100
1
1
1
ZERO
ZERO
ZERO
THROUGHPUT – kSPS
SEQ1
SEQ1
SEQ1
t
t
t
9
9
9
150
2
2
2
2 IDENTIFICATION
2 IDENTIFICATION
2 IDENTIFICATION
ADD1
ADD1
ADD1
DONTC
DONTC
DONTC
200
BITS
BITS
BITS
Figure 16. AD7904 Serial Interface Timing Diagram
Figure 17. AD7914 Serial Interface Timing Diagram
Figure 18. AD7924 Serial Interface Timing Diagram
3
3
3
V
ADD0
ADD0
ADD0
t
t
t
DD
4
4
4
DONTC
DONTC
DONTC
250
= 3V
4
4
4
DB7
DB11
DB9
300
ADD1
ADD1
t
t
t
ADD1
6
6
6
5
5
5
350
t
t
t
DB10
7
7
7
DB6
DB8
t
t
t
CONVERT
CONVERT
CONVERT
ADD0
ADD0
ADD0
t
t
t
10
10
10
6
6
6
–21–
SERIAL INTERFACE
Figures 16, 17, and 18 show the detailed timing diagrams for
serial interfacing to the AD7904, AD7914, and AD7924,
respectively. The serial clock provides the conversion clock and
also controls the transfer of information to and from the
AD7904/AD7914/AD7924 during each conversion.
The CS signal initiates the data transfer and conversion process.
The falling edge of CS puts the track and hold into hold mode,
takes the bus out of three-state and the analog input is sampled
at this point. The conversion is also initiated at this point and
will require 16 SCLK cycles to complete. The track and hold
will go back into track on the fourteenth SCLK falling edge as
shown in Figures 16, 17, and 18 at Point B. On the sixteenth
SCLK falling edge, the DOUT line will go back into three-state.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion will be terminated, the DOUT line will go back
into three-state, and the Control Register will not be updated;
otherwise DOUT returns to three-state on the sixteenth SCLK
falling edge as shown in Figures 16, 17, and 18.
11
11
11
DB0
DB2
DB4
CODING
CODING
CODING
12
12
12
ZERO
DB3
DB1
DONTC
DONTC
DONTC
13
13
13
4 TRAILING ZEROS
ZERO
DB0
DB2
DONTC
DONTC
DONTC
AD7904/AD7914/AD7924
B
B
B
14
14
14
t
t
t
5
5
5
2 TRAILING ZEROS
ZERO
ZERO
DB1
DONTC
DONTC
DONTC
15
15
15
t
t
t
ZERO
ZERO
8
8
8
DB0
DONTC
DONTC
DONTC
16
16
16
t
t
t
11
11
11
THREE-
STATE
THREE-
STATE
THREE-
STATE
t
t
t
QUIET
QUIET
QUIET