CS5550-ISZ Cirrus Logic Inc, CS5550-ISZ Datasheet - Page 22

• Manufacturer Part Number: CS5550-ISZ
• Description: IC ADC 2CH LOW-COST 24SSOP
• Manufacturer: Cirrus Logic Inc

Specifications of CS5550-ISZ

• Number Of Converters: 2
• Package / Case: 24-SSOP
• Number Of Bits: 2
• Sampling Rate (per Second): 4k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 2
• Architecture: Delta-Sigma
• Conversion Rate: 4 KSPs
• Resolution: 24 bit
• Input Type: Voltage
• Interface Type: Serial (3-Wire)
• Voltage Reference: 2.5 V
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Voltage: 3.3 V to 5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1119-5

5.5 OUT
5.6 FILT
5.7 Status Register and Mask Register
22
MSB
MSB
-(2
2
-1
Address:
0
Address:
Default** = 0x000000 (Status [Clear] Register
The Status [Clear] Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause
the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature
the user can simply write back to the Status [Clear] Register to clear the bits that have been seen, without con-
cern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt (at the time that the
status bit is asserted), the status bit will still be set in (both of) the Status Registers so the user can poll the status.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.
Address:
These signed registers contain the last value of the measured results of AIN1 and AIN2. The results will be with-
in the range of -1.0 ≤ AIN1,AIN2 < 1.0. The value is represented in two's complement notation, with the binary
point place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two
least significant bits, (located at the far right-side) have no meaning, and will always have a value of “0”.
Address:
These unsigned registers contain the last values of FILT
0.0 ≤ FILT
the left of the MSB. These results are updated after each computation cycle.
DRDY
DRDY
OR1, OR2
)
23
15
7
2
2
-1
-2
1
1
, FILT
and OUT
1
,FILT
0x000000 (Mask Register)
2
2
-2
-3
FOR1
15 (Status [Clear] Register)
26 (Mask Register)
2
22
14
dicate the end of computation cycles. When running calibrations, this bit indicates that the cal-
ibration sequence has completed, and the results have been stored in the offset or gain
Data Ready. When running in single or continuous conversion acquisition mode, this bit will in-
AIN Output Out of Range. Set when the magnitude of the calibrated output is too large or too
2
6
Unsigned Output Register
< 1.0. The value is represented in (unsigned) binary notation, with the binary point place to
7 (AIN1 Output Register)
8 (AIN2 Output Register)
11 (AIN1 Filtered Output Register)
12 (AIN2 Filtered Output Register)
2
2
2
-3
-4
Output Registers
2
2
-4
-5
FOR2
21
13
5
2
2
-5
-6
2
2
-6
-7
CRDY
OD2
20
12
4
2
2
-7
-8
.....
.....
1
and FILT
OD1
19
11
3
2
2
-17
-18
2
. The results are in the range of
2
2
-18
-19
18
10
2
2
2
-19
-20
2
2
-20
-21
OR1
17
9
1
2
2
-21
-22
CS5550
2
2
-22
-23
DS630F1
OR2
16
IC
8
0
LSB
LSB
2
2
-23
-24