AD7992BRMZ-1 Analog Devices Inc, AD7992BRMZ-1 Datasheet - Page 20

• Manufacturer Part Number: AD7992BRMZ-1
• Description: IC ADC 12BIT 2CHAN I2C 10-MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7992BRMZ-1

• Data Interface: I²C, Serial
• Operating Temperature: -40°C ~ 125°C
• Number Of Bits: 12
• Sampling Rate (per Second): 79k
• Number Of Converters: 1
• Power Dissipation (max): 2.2mW
• Voltage Supply Source: Single Supply
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• Resolution (bits): 12bit
• Input Channel Type: Single Ended
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 1.4mA
• No. Of Pins: 10
• Sampling Rate: 188kSPS
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7992CB - BOARD EVALUATION FOR AD7992
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7992
SERIAL INTERFACE
Control of the AD7992 is carried out via the I
serial bus. The AD7992 is connected to this bus as a slave device
under the control of a master device, such as the processor.
SERIAL BUS ADDRESS
Like all I
address. The 3 MSBs of this address for the AD7992 are set to
010. The device comes in two versions, the AD7992-0 and the
AD7992-1. The two versions have three different I
available, which are selected by either tying the address select
pin, AS, to AGND or V
Table 6). By giving different addresses for the two versions, up
to five AD7992 devices can be connected to a single serial bus,
or the addresses can be set to avoid conflicts with other devices
on the bus.
The serial bus protocol operates as follows.
The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line, SCL, remains high.
This indicates that an address/data stream follows. All slave
peripherals connected to the serial bus respond to the START
condition and shift in the next eight bits, consisting of a 7-bit
address (MSB first) plus an R/ W bit that determines the
direction of the data transfer—that is, whether data is written to
or read from the slave device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit. All other devices on the bus remain idle while the selected
device waits for data to be read from or written to it. If the R/ W
bit is a 0, the master writes to the slave device. If the R/ W bit is
a 1, the master reads from the slave device.
2
C-compatible devices, the AD7992 has a 7-bit serial
DD
, or by letting the pin float (refer to
2
C-compatible
2
C addresses
Rev. 0 | Page 20 of 28
Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the receiver of data. Transitions on the data line must occur
during the low period of the clock signal and remain stable
during the high period, because a low-to-high transition when
the clock is high may be interpreted as a STOP signal.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a STOP condition. In
read mode, the master device pulls the data line high during the
low period before the ninth clock pulse. This is known as no
acknowledge. The master then takes the data line low during
the low period before the 10th clock pulse, then high during the
10th clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.