AD7798BRUZ Analog Devices Inc, AD7798BRUZ Datasheet - Page 6

• Manufacturer Part Number: AD7798BRUZ
• Description: IC ADC 16BIT SIG-DEL 3CH 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7798BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Bits: 16
• Sampling Rate (per Second): 470
• Number Of Converters: 1
• Power Dissipation (max): 2mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 16bit
• Sampling Rate: 470SPS
• Input Channel Type: Single Ended
• Supply Voltage Range - Analog: 2.7V To 5.25V
• Supply Voltage Range - Digital: 2.7V To 5.25V
• Number Of Elements: 1
• Resolution: 16Bit
• Architecture: Delta-Sigma
• Sample Rate: 0.47KSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±2.5V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.25V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 2mW
• Integral Nonlinearity Error: ±15ppm of FSR
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7798EB - BOARD EVALUATION FOR AD7798
• Lead Free Status / Rohs Status: Compliant

AD7798/AD7799
TIMING CHARACTERISTICS
AV
Table 2.
Parameter
t
t
Read Operation
Write Operation
1
2
3
4
5
6
3
4
Sample tested during initial release to ensure compliance. All input signals are specified with t
See Figure 3 and Figure 4.
These times are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
SCLK active edge is the falling edge of SCLK.
These times are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured time is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
RDY returns high after a read of the ADC. In single-conversion mode and continuous-conversion mode, data can be reread, if required, while RDY is high, but care
should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read only once.
t
t
t
t
t
t
t
t
t
1
2
5
6
7
8
9
10
11
DD
3
5, 6
= 2.7 V to 5.25 V, DV
1, 2
Limit at T
100
100
0
60
80
0
60
80
10
80
0
10
0
30
25
0
DD
= 2.7 V to 5.25 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DV
MIN
, T
MAX
(B Version)
OUTPUT
Figure 2. Load Circuit for Timing Characterization
PIN
TO
50pF
Rev. A | Page 6 of 28
Unit
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
I
100µA WITH DV
I
100µA WITH DV
SINK
SOURCE
(1.6mA WITH DV
(200µA WITH DV
1.6V
Conditions/Comments
SCLK high pulse width
SCLK low pulse width
CS falling edge to DOUT/RDY active time
DV
DV
SCLK active edge to data valid delay
DV
DV
Bus relinquish time after CS inactive edge
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high
CS falling edge to SCLK active edge setup time
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
DD
DD
R
= t
DD
DD
DD
DD
= 3V)
= 3V)
F
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
= 4.75 V to 5.25 V
= 2.7 V to 3.6 V
DD
= 5 ns (10% to 90% of DV
= 5V,
DD
= 5V,
OL
DD
or V
, unless otherwise noted.
DD
OH
) and timed from a voltage level of 1.6 V.
limits.
4
4