AD7767BRUZ-2 Analog Devices Inc, AD7767BRUZ-2 Datasheet - Page 19

• Manufacturer Part Number: AD7767BRUZ-2
• Description: ADC 24BIT 32KSPS SAR 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7767BRUZ-2

• Data Interface: Serial
• Number Of Bits: 24
• Sampling Rate (per Second): 32k
• Number Of Converters: 1
• Power Dissipation (max): 18mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 128kSPS
• Input Channel Type: Differential, Single Ended
• Supply Voltage Range - Analog: 2.375V To 2.625V
• Number Of Elements: 1
• Resolution: 24Bit
• Architecture: SAR
• Sample Rate: 32KSPS
• Input Polarity: Unipolar
• Input Type: Voltage
• Rated Input Volt: ±2.5V
• Differential Input: Yes
• Power Supply Requirement: Analog and Digital
• Single Supply Voltage (typ): 2.5V
• Single Supply Voltage (min): 2.375V
• Single Supply Voltage (max): 2.625V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 10.5mW
• Integral Nonlinearity Error: ±7.6ppm
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 16
• Package Type: TSSOP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7767EDZ - BOARD EVAL AD7767 128KSPS 108DBEVAL-AD7767-1EDZ - BOARD EVAL AD7767-1 64KSPS 111DB
• Lead Free Status / Rohs Status: Compliant

DAISY-CHAIN MODE CONFIGURATION AND TIMING DIAGRAMS
SDI (A) = SDO (B)
SDI (B) = SDO (C)
SDI (C) = SDO (D)
SDI (A) = SDO (B)
DRDY (A)
DRDY (A)
SDO (A)
SDO (A)
MCLK
MCLK
SCLK
SCLK
CS
CS
Figure 37. Daisy-Chain Timing Diagram (n = 1 for AD7767, n = 2 for AD7767-1, n = 4 for AD7767-2) When Driving the AD7767
SYNC/PD
CS
SCLK
MCLK
SDI
CS
SDI
SCLK
24 ×
AD7767 (A)
AD7767 (B)
AD7767 (C)
AD7767 (D)
MSB (A)
MSB (B)
1
t
AD7767
16
SYNC/PD
MCLK
t
SCLK
(D)
SDO
t
Figure 36. Daisy-Chain Configuration with Four AD7767 Devices
1
17
Figure 38. Daisy-Chain SDI Setup and Hold Timing
24 ×
AD7767 (B)
AD7767 (C)
AD7767 (D)
t
CS
SDI
SCLK
SCLK
LSB (A) MSB (B)
LSB (B) MSB (C)
AD7767
SYNC/PD
MCLK
(C)
Rev. C | Page 19 of 24
SDO
24 ×
AD7767 (C)
AD7767 (D)
t
SCLK
CS
SDI
SCLK
AD7767
SYNC/PD
MCLK
(B)
LSB (B)
LSB (C)
SDO
24 ×
AD7767 (D)
MSB (C)
MSB (D)
t
SCLK
CS
SDI
SCLK
AD7767
SYNC/PD
MCLK
(A)
8 × n
DRDY
SDO
LSB (C)
LSB (D)
AD7767 (A)
AD7767 (B)
AD7767 (C)
AD7767 (D)
AD7767