MAX1238EEE+ Maxim Integrated Products, MAX1238EEE+ Datasheet - Page 5

• Manufacturer Part Number: MAX1238EEE+
• Description: IC ADC 12-BIT 94KSPS 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1238EEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 666.7mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 12
• Architecture: SAR
• Conversion Rate: 94.4 KSPs
• Resolution: 12 bit
• Interface Type: I2C
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
4.096V (MAX1236/MAX1238), f
T
Note 1: For DC accuracy, the MAX1236/MAX1238 are tested at V
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V
Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µV
Note 9: Measured as for the MAX1237/MAX1239
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (C
Serial Clock Frequency
Hold Time, Repeated START
Condition (Sr)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time
Data Setup Time
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal after
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
A
DD
= +25°C, see Tables 1–5 for programming notation.)
= 2.7V to 3.6V (MAX1237/MAX1239), V
devices are configured for unipolar, single-ended inputs.
offsets have been calibrated.
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit ).
PARAMETER
⎡
⎢
⎢
⎣
[
V
FS
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
( .
3 6
4-/12-Channel, 2-Wire Serial, 12-Bit ADCs
_______________________________________________________________________________________
V
( .
)
3 6
−
V
FS
V
−
( .
2 7
2 7
.
V
V
)
SCL
)
]
SYMBOL
t
t
t
t
t
HD
HD, STA
SU
SU
SU
×
f
t
t
t
t
SCLH
HIGH
t
RCL1
t
t
LOW
RDA
RCL
FDA
t
FCL
C
,
,
SP
,
,
= 1.7MHz, T
2
V
B
STA
DAT
DAT
STO
N
REF
−
DD
1
⎤
⎥
⎥
⎦
(Note 13)
(Note 10)
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 10 and 13)
= 4.5V to 5.5V (MAX1236/MAX1238), V
A
= T
B
= 400pF, Note 12)
MIN
CONDITIONS
DD
to T
DD
DD
DD
DD
= 5V and the MAX1237/MAX1239 are tested at V
- 0.7V
- 0.7V
- 0.7V
- 0.7V
MAX
, unless otherwise noted. Typical values are at
DD
DD
DD
DD
(Note 11)
P-P
.
REF
= 2.048V (MAX1237/MAX1239), V
DD
MIN
160
320
120
160
160
.
10
20
20
20
20
20
0
0
TYP
MAX
150
160
160
160
400
1.7
80
80
10
DD
= 3V. All
UNITS
MHz
REF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
=