MAX1247BCEE+ Maxim Integrated Products, MAX1247BCEE+ Datasheet - Page 13

• Manufacturer Part Number: MAX1247BCEE+
• Description: IC ADC SRL 4CH 12BIT 2.7V 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1247BCEE+

• Number Of Bits: 12
• Sampling Rate (per Second): 133k
• Data Interface: MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 667mW
• Voltage Supply Source: Single Supply
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Number Of Adc Inputs: 4
• Architecture: SAR
• Conversion Rate: 133 KSPs
• Resolution: 12 bit
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Voltage Reference: External
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3 V
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

In internal clock mode, the MAX1246/MAX1247 generate
their own conversion clocks internally. This frees the µP
from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
Figure 5. 24-Clock External Clock Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with f
Figure 6. Detailed Serial-Interface Timing
SSTRB
DOUT
A/D STATE
SCLK
DIN
CS
DOUT
SCLK
DIN
CS
START
1
t
CSH
SEL2 SEL1 SEL0
______________________________________________________________________________________
IDLE
t
DV
t
CSS
RB1
4
t
DS
UNI/
BIP
t
DH
SGL/
(f
DIF
ACQUISITION
SCLK
1.5µs
t
ACQ
PD1
= 2MHz)
PD0
8
t
CL
Internal Clock
Serial 12-Bit ADCs in QSOP-16
+2.7V, Low-Power, 4-Channel,
t
CH
MSB
B11
B10
• • •
• • •
• • •
• • •
B9
12
RB2
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1246/MAX1247 and three-states DOUT, but it
does not adversely affect an internal clock mode
B8
CONVERSION
B7
B6
B5
16
t
DO
B4
B3
B2
t
CSH
B1
20
RB3
LSB
B0
FILLED WITH
ZEROS
t
TR
IDLE
SCLK
≤ 2MHz)
24
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