LTC2173IUKG-12#PBF Linear Technology, LTC2173IUKG-12#PBF Datasheet - Page 22

• Manufacturer Part Number: LTC2173IUKG-12#PBF
• Description: IC ADC 12BIT SER 80MSPS 52-QFN
• Manufacturer: Linear Technology

Specifications of LTC2173IUKG-12#PBF

• Number Of Bits: 12
• Sampling Rate (per Second): 80M
• Data Interface: Serial, SPI™
• Number Of Converters: 4
• Power Dissipation (max): 446mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 52-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LTC2175-12/
LTC2174-12/LTC2173-12
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be
taken above V
range is from 1.1V to 1.6V. In the differential encode
mode, ENC
avoid falsely triggering the single-ended encode mode.
For good jitter performance ENC
and fall times.
The single-ended encode mode should be used with CMOS
encode inputs. To select this mode, ENC
to ground and ENC
input. ENC
to 3.3V CMOS logic levels can be used. The ENC
22
APPLICATIONS INFORMATION
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
0.1μF
0.1μF
+
–
can be taken above V
should stay at least 200mV above ground to
Figure 12. Sinusoidal Encode Drive
DD
T1
(up to 3.6V), and the common mode
50Ω
50Ω
+
is driven with a square wave encode
0.1μF
100Ω
+
DD
should have fast rise
ENC –
ENC
(up to 3.6V) so 1.8V
+
LTC2175-12
–
is connected
+
217512 F12
threshold
is 0.9V. For good jitter performance ENC
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
The encode clock is multiplied by an internal phase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25μs to lock onto the input clock.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
Figure 13. PECL or LVDS Encode Drive
PECL OR
CLOCK
LVDS
0.1μF
0.1μF
ENC
ENC
+
–
LTC2175-12
217512 F13
+
should have fast
21754312f